1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import coupledL2.PrefetchCtrlFromCore 24import device.MsiInfoBundle 25import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 26import freechips.rocketchip.tile.HasFPUParameters 27import system.HasSoCParameter 28import utils._ 29import utility._ 30import utility.mbist.{MbistInterface, MbistPipeline} 31import utility.sram.{SramBroadcastBundle, SramMbistBundle, SramHelper} 32import xiangshan.frontend._ 33import xiangshan.backend._ 34import xiangshan.backend.fu.PMPRespBundle 35import xiangshan.backend.trace.TraceCoreInterface 36import xiangshan.mem._ 37import xiangshan.cache.mmu._ 38import xiangshan.cache.mmu.TlbRequestIO 39import scala.collection.mutable.ListBuffer 40 41abstract class XSModule(implicit val p: Parameters) extends Module 42 with HasXSParameter 43 with HasFPUParameters 44 45//remove this trait after impl module logic 46trait NeedImpl { 47 this: RawModule => 48 protected def IO[T <: Data](iodef: T): T = { 49 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 50 val io = chisel3.IO(iodef) 51 io <> DontCare 52 io 53 } 54} 55 56abstract class XSBundle(implicit val p: Parameters) extends Bundle 57 with HasXSParameter 58 59abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 60 with HasXSParameter 61{ 62 override def shouldBeInlined: Boolean = false 63 // outer facing nodes 64 val frontend = LazyModule(new Frontend()) 65 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 66 val backend = LazyModule(new Backend(backendParams)) 67 68 val memBlock = LazyModule(new MemBlock) 69 70 memBlock.inner.frontendBridge.icache_node := frontend.inner.icache.clientNode 71 memBlock.inner.frontendBridge.instr_uncache_node := frontend.inner.instrUncache.clientNode 72 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 73 frontend.inner.icache.ctrlUnitOpt.get.node := memBlock.inner.frontendBridge.icachectrl_node 74 } 75} 76 77class XSCore()(implicit p: config.Parameters) extends XSCoreBase 78 with HasXSDts 79{ 80 lazy val module = new XSCoreImp(this) 81} 82 83class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 84 with HasXSParameter 85 with HasSoCParameter { 86 val io = IO(new Bundle { 87 val hartId = Input(UInt(hartIdLen.W)) 88 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 89 val clintTime = Input(ValidIO(UInt(64.W))) 90 val reset_vector = Input(UInt(PAddrBits.W)) 91 val cpu_halt = Output(Bool()) 92 val l2_flush_done = Input(Bool()) 93 val l2_flush_en = Output(Bool()) 94 val power_down_en = Output(Bool()) 95 val cpu_critical_error = Output(Bool()) 96 val resetInFrontend = Output(Bool()) 97 val traceCoreInterface = new TraceCoreInterface 98 val l2PfCtrl = Output(new PrefetchCtrlFromCore) 99 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) 100 val beu_errors = Output(new XSL1BusErrors()) 101 val l2_hint = Input(Valid(new L2ToL1Hint())) 102 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 103 val l2_pmp_resp = new PMPRespBundle 104 val l2PfqBusy = Input(Bool()) 105 val debugTopDown = new Bundle { 106 val robTrueCommit = Output(UInt(64.W)) 107 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 108 val l2MissMatch = Input(Bool()) 109 val l3MissMatch = Input(Bool()) 110 } 111 val topDownInfo = Input(new Bundle { 112 val l2Miss = Bool() 113 val l3Miss = Bool() 114 }) 115 val sramTest = new Bundle() { 116 val mbist = Option.when(hasMbist)(Input(new SramMbistBundle)) 117 val mbistReset = Option.when(hasMbist)(Input(new DFTResetSignals())) 118 val sramCtl = Option.when(hasSramCtl)(Input(UInt(64.W))) 119 } 120 }) 121 122 dontTouch(io.l2_flush_done) 123 dontTouch(io.l2_flush_en) 124 dontTouch(io.power_down_en) 125 126 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 127 128 val frontend = outer.frontend.module 129 val backend = outer.backend.module 130 val memBlock = outer.memBlock.module 131 132 frontend.io.hartId := memBlock.io.inner_hartId 133 frontend.io.reset_vector := memBlock.io.inner_reset_vector 134 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 135 frontend.io.backend <> backend.io.frontend 136 frontend.io.sfence <> backend.io.frontendSfence 137 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 138 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 139 frontend.io.fencei <> backend.io.fenceio.fencei 140 141 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 142 143 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 144 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 145 sink.valid := source.valid 146 sink.bits := 0.U.asTypeOf(sink.bits) 147 sink.bits.robIdx := source.bits.uop.robIdx 148 sink.bits.ssid := source.bits.uop.ssid 149 sink.bits.storeSetHit := source.bits.uop.storeSetHit 150 // The other signals have not been used 151 } 152 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 153 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 154 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 155 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 156 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 157 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 158 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 159 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 160 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 161 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 162 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 163 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 164 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 165 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 166 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 167 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 168 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 169 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 170 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 171 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 172 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 173 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 174 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 175 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 176 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 177 178 // memblock error exception writeback, 1 cycle after normal writeback 179 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 180 181 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 182 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 183 backend.io.mem.exceptionAddr.isForVSnonLeafPTE := memBlock.io.mem_to_ooo.lsqio.isForVSnonLeafPTE 184 backend.io.mem.debugLS := memBlock.io.debug_ls 185 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 186 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 187 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 188 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 189 190 backend.io.perf.frontendInfo := frontend.io.frontendInfo 191 backend.io.perf.memInfo := memBlock.io.memInfo 192 backend.io.perf.perfEventsFrontend := frontend.io_perf 193 backend.io.perf.perfEventsLsu := memBlock.io_perf 194 backend.io.perf.perfEventsHc := memBlock.io.inner_hc_perfEvents 195 backend.io.perf.perfEventsBackend := DontCare 196 backend.io.perf.retiredInstr := DontCare 197 backend.io.perf.ctrlInfo := DontCare 198 199 backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo 200 201 // top -> memBlock 202 memBlock.io.fromTopToBackend.clintTime := io.clintTime 203 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 204 memBlock.io.hartId := io.hartId 205 memBlock.io.l2_flush_done := io.l2_flush_done 206 memBlock.io.outer_reset_vector := io.reset_vector 207 memBlock.io.outer_hc_perfEvents := io.perfEvents 208 // frontend -> memBlock 209 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 210 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 211 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 212 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 213 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 214 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 215 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 216 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 217 218 // By default, instructions do not have exceptions when they enter the function units. 219 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 220 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 221 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 222 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 223 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 224 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 225 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 226 227 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 228 229 memBlock.io.redirect := backend.io.mem.redirect 230 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 231 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 232 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 233 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 234 memBlock.io.ooo_to_mem.lsqio.pendingMMIOld := backend.io.mem.robLsqIO.pendingMMIOld 235 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 236 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 237 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 238 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 239 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 240 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 241 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 242 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 243 244 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 245 memBlock.io.l2_hint.valid := io.l2_hint.valid 246 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 247 memBlock.io.l2_tlb_req <> io.l2_tlb_req 248 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 249 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 250 memBlock.io.l2PfqBusy := io.l2PfqBusy 251 252 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 253 254 // top-down info 255 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 256 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 257 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 258 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 259 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 260 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 261 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 262 memBlock.io.debugRolling := backend.io.debugRolling 263 264 io.cpu_halt := memBlock.io.outer_cpu_halt 265 io.l2_flush_en := memBlock.io.outer_l2_flush_en 266 io.power_down_en := memBlock.io.outer_power_down_en 267 io.cpu_critical_error := memBlock.io.outer_cpu_critical_error 268 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 269 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 270 io.beu_errors.l2 <> DontCare 271 io.l2PfCtrl := backend.io.mem.csrCtrl.pf_ctrl.toL2PrefetchCtrl() 272 273 memBlock.io.resetInFrontendBypass.fromFrontend := frontend.io.resetInFrontend 274 io.resetInFrontend := memBlock.io.resetInFrontendBypass.toL2Top 275 memBlock.io.traceCoreInterfaceBypass.fromBackend <> backend.io.traceCoreInterface 276 io.traceCoreInterface <> memBlock.io.traceCoreInterfaceBypass.toL2Top 277 memBlock.io.topDownInfo.fromL2Top.l2Miss := io.topDownInfo.l2Miss 278 memBlock.io.topDownInfo.fromL2Top.l3Miss := io.topDownInfo.l3Miss 279 memBlock.io.topDownInfo.toBackend.noUopsIssued := backend.io.topDownInfo.noUopsIssued 280 backend.io.topDownInfo.lqEmpty := memBlock.io.topDownInfo.toBackend.lqEmpty 281 backend.io.topDownInfo.sqEmpty := memBlock.io.topDownInfo.toBackend.sqEmpty 282 backend.io.topDownInfo.l1Miss := memBlock.io.topDownInfo.toBackend.l1Miss 283 backend.io.topDownInfo.l2TopMiss.l2Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l2Miss 284 backend.io.topDownInfo.l2TopMiss.l3Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l3Miss 285 286 287 if (debugOpts.ResetGen) { 288 backend.reset := memBlock.io.reset_backend 289 frontend.reset := backend.io.frontendReset 290 } 291 292 if (hasMbist) { 293 memBlock.io.sramTestBypass.fromL2Top.mbist.get := io.sramTest.mbist.get 294 memBlock.io.sramTestBypass.fromL2Top.mbistReset.get := io.sramTest.mbistReset.get 295 frontend.io.sramTest.mbist.get := memBlock.io.sramTestBypass.toFrontend.mbist.get 296 frontend.io.sramTest.mbistReset.get := memBlock.io.sramTestBypass.toFrontend.mbistReset.get 297 backend.io.sramTest.mbist.get := memBlock.io.sramTestBypass.toBackend.mbist.get 298 backend.io.sramTest.mbistReset.get := memBlock.io.sramTestBypass.toBackend.mbistReset.get 299 } 300 301 if (hasSramCtl) { 302 memBlock.io.sramTestBypass.fromL2Top.sramCtl.get := io.sramTest.sramCtl.get 303 frontend.io.sramTest.sramCtl.get := memBlock.io.sramTestBypass.toFrontend.sramCtl.get 304 } 305} 306