1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.ExceptionNO 6import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState, XtvecBundle} 7import xiangshan.backend.fu.NewCSR.CSRDefines.XtvecMode 8import xiangshan.backend.fu.NewCSR.CSRBundleImplicitCast._ 9 10 11class TrapHandleModule extends Module { 12 val io = IO(new TrapHandleIO) 13 14 private val trapInfo = io.in.trapInfo 15 private val privState = io.in.privState 16 private val mstatus = io.in.mstatus 17 private val vsstatus = io.in.vsstatus 18 private val mnstatus = io.in.mnstatus 19 private val mideleg = io.in.mideleg.asUInt 20 private val hideleg = io.in.hideleg.asUInt 21 private val medeleg = io.in.medeleg.asUInt 22 private val hedeleg = io.in.hedeleg.asUInt 23 private val mvien = io.in.mvien.asUInt 24 private val hvien = io.in.hvien.asUInt 25 private val virtualInterruptIsHvictlInject = io.in.virtualInterruptIsHvictlInject 26 27 private val hasTrap = trapInfo.valid 28 private val hasNMI = hasTrap && trapInfo.bits.nmi 29 private val hasIR = hasTrap && trapInfo.bits.isInterrupt 30 private val hasEX = hasTrap && !trapInfo.bits.isInterrupt 31 32 private val exceptionVec = io.in.trapInfo.bits.trapVec 33 private val intrVec = io.in.trapInfo.bits.intrVec 34 private val hasEXVec = Mux(hasEX, exceptionVec, 0.U) 35 private val hasIRVec = Mux(hasIR, intrVec, 0.U) 36 37 private val irToHS = io.in.trapInfo.bits.irToHS 38 private val irToVS = io.in.trapInfo.bits.irToVS 39 40 private val highestPrioEXVec = Wire(Vec(64, Bool())) 41 highestPrioEXVec.zipWithIndex.foreach { case (excp, i) => 42 if (ExceptionNO.priorities.contains(i)) { 43 val higherEXSeq = ExceptionNO.getHigherExcpThan(i) 44 excp := ( 45 higherEXSeq.nonEmpty.B && Cat(higherEXSeq.map(num => !hasEXVec(num))).andR || 46 higherEXSeq.isEmpty.B 47 ) && hasEXVec(i) 48 } else 49 excp := false.B 50 } 51 52 private val highestPrioIR = hasIRVec.asUInt 53 private val highestPrioEX = highestPrioEXVec.asUInt 54 55 private val mEXVec = highestPrioEX 56 private val hsEXVec = highestPrioEX & medeleg 57 private val vsEXVec = highestPrioEX & medeleg & hedeleg 58 59 // nmi handle in MMode only and default handler is mtvec 60 private val mHasIR = hasIR 61 private val hsHasIR = hasIR && irToHS & !hasNMI 62 private val vsHasIR = hasIR && irToVS & !hasNMI 63 64 private val mHasEX = mEXVec.orR 65 private val hsHasEX = hsEXVec.orR 66 private val vsHasEX = vsEXVec.orR 67 68 private val mHasTrap = mHasEX || mHasIR 69 private val hsHasTrap = hsHasEX || hsHasIR 70 private val vsHasTrap = vsHasEX || vsHasIR 71 72 private val handleTrapUnderHS = !privState.isModeM && hsHasTrap 73 private val handleTrapUnderVS = privState.isVirtual && vsHasTrap 74 private val handleTrapUnderM = !handleTrapUnderVS && !handleTrapUnderHS 75 76 // Todo: support more interrupt and exception 77 private val exceptionRegular = OHToUInt(highestPrioEX) 78 private val interruptNO = highestPrioIR 79 private val exceptionNO = Mux(trapInfo.bits.singleStep, ExceptionNO.breakPoint.U, exceptionRegular) 80 81 private val causeNO = Mux(hasIR, interruptNO, exceptionNO) 82 83 // sm/ssdbltrp 84 private val m_EX_DT = handleTrapUnderM && mstatus.MDT.asBool && hasTrap 85 private val s_EX_DT = handleTrapUnderHS && mstatus.SDT.asBool && hasTrap 86 private val vs_EX_DT = handleTrapUnderVS && vsstatus.SDT.asBool && hasTrap 87 88 private val dbltrpToMN = m_EX_DT && mnstatus.NMIE.asBool // NMI not allow double trap 89 private val hasDTExcp = m_EX_DT || s_EX_DT || vs_EX_DT 90 91 private val trapToHS = handleTrapUnderHS && !s_EX_DT && !vs_EX_DT 92 private val traptoVS = handleTrapUnderVS && !vs_EX_DT 93 94 private val xtvec = MuxCase(io.in.mtvec, Seq( 95 traptoVS -> io.in.vstvec, 96 trapToHS -> io.in.stvec 97 )) 98 private val adjustinterruptNO = Mux( 99 InterruptNO.getVS.map(_.U === interruptNO).reduce(_ || _) && vsHasIR, 100 interruptNO - 1.U, // map VSSIP, VSTIP, VSEIP to SSIP, STIP, SEIP 101 interruptNO, 102 ) 103 private val pcFromXtvec = Cat(xtvec.addr.asUInt + Mux(xtvec.mode === XtvecMode.Vectored && hasIR, adjustinterruptNO(5, 0), 0.U), 0.U(2.W)) 104 105 io.out.entryPrivState := MuxCase(default = PrivState.ModeM, mapping = Seq( 106 traptoVS -> PrivState.ModeVS, 107 trapToHS -> PrivState.ModeHS, 108 )) 109 110 io.out.causeNO.Interrupt := hasIR 111 io.out.causeNO.ExceptionCode := causeNO 112 io.out.pcFromXtvec := pcFromXtvec 113 io.out.hasDTExcp := hasDTExcp 114 io.out.dbltrpToMN := dbltrpToMN 115 116} 117 118class TrapHandleIO extends Bundle { 119 val in = Input(new Bundle { 120 val trapInfo = ValidIO(new Bundle { 121 val trapVec = UInt(64.W) 122 val nmi = Bool() 123 val intrVec = UInt(8.W) 124 val isInterrupt = Bool() 125 val singleStep = Bool() 126 // trap to x mode 127 val irToHS = Bool() 128 val irToVS = Bool() 129 }) 130 val privState = new PrivState 131 val mstatus = new MstatusBundle 132 val vsstatus = new SstatusBundle 133 val mnstatus = new MnstatusBundle 134 val mideleg = new MidelegBundle 135 val medeleg = new MedelegBundle 136 val hideleg = new HidelegBundle 137 val hedeleg = new HedelegBundle 138 val mvien = new MvienBundle 139 val hvien = new HvienBundle 140 // trap vector 141 val mtvec = Input(new XtvecBundle) 142 val stvec = Input(new XtvecBundle) 143 val vstvec = Input(new XtvecBundle) 144 // virtual interrupt is hvictl inject 145 val virtualInterruptIsHvictlInject = Input(Bool()) 146 }) 147 148 val out = new Bundle { 149 val entryPrivState = new PrivState 150 val causeNO = new CauseBundle 151 val dbltrpToMN = Bool() 152 val hasDTExcp = Bool() 153 val pcFromXtvec = UInt() 154 } 155}