fix(csr): fix trap handle bundle format (#4579)

area(csr): intr NO bits is reduced from 64 to 8

fix(NewCSR): fix the error of trap entry PC in vs mode interrupts (#4064)

* calculate VSSIP, VSTIP, VSEIP trap entry in VSmode should use vscause after mapping

fix(intr): fix interrupt trap to which mode to handle

fix(csr): fix interrupt code use xtopi.IID replace instread of xip & xie

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

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* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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fix(csr): add support virtual interrupt for hvictl csr injection

feat(riscv64): support RISC-V Smrnmi extension (#3480)

Trigger: refactor trigger information in pipeline. (#3403)

CSR: fix custom IRQ injection mechanism

* The injected interrupts for HS mode can set some bits in mIRVec and hsIRVec.
* `mIRVec` holds the highest priority interrupt numbered from 1 to 63. Only int

CSR: fix custom IRQ injection mechanism

* The injected interrupts for HS mode can set some bits in mIRVec and hsIRVec.
* `mIRVec` holds the highest priority interrupt numbered from 1 to 63. Only interrupt 1~13 can trap in M mode. And interrupt 14~63 must trap in HS mode or VS mode, since bits in mideleg(63,14) are read-only 0.
* `hsIRVec` holds the mip parts(by mIRVec & mideleg) and mvip parts(by mIRVec & ~mideleg & mvien) interrupts.
* `vsIRVec` holds the sip|hip parts(by hsIRVec & hideleg) and hvip parts(by hsIRVec & ~hideleg & hvien) interrupts.

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CSR: add custom IRQ injection mechanism (#3338)

* All major interrupts have been splited into 7 groups
* Custom highest group
* Local high group
* Custom middle-high group
* Priviledge a

CSR: add custom IRQ injection mechanism (#3338)

* All major interrupts have been splited into 7 groups
* Custom highest group
* Local high group
* Custom middle-high group
* Priviledge architecture group
* Custom middle-low group
* Local low group
* Custom lowest group

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NewCSR: fix highest EX/IR produce

NewCSR: VS level interrupt should map as VS level in higher privilege

NewCSR: Refactor CSR about Debug

* add CSR: trigger csr & debug csr

* add CSR event: TrapEntryDEvent & DretEvent

* fixed trigger's comparison func between Consecutive pc and tdada2

NewCSR: only exception raised in VS/VU mode can be delegated to VS mode

NewCSR: fix trapHandle intrVec

* we store intrVec in newCSR reg when interrupt valid

NewCSR: fix pcFromXtvec in trapHandle

* We should use xtvec.mode instead of mtvec.mode to compare with XtvecMode.vectored when a trap occurs

NewCSR: fix target pc of trap entry event

NewCSR: add TrapHandleModule to handle trap delegation and dispatch traps