1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.ExceptionNO 6import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState, XtvecBundle} 7import xiangshan.backend.fu.NewCSR.CSRDefines.XtvecMode 8import xiangshan.backend.fu.NewCSR.CSRBundleImplicitCast._ 9 10 11class TrapHandleModule extends Module { 12 val io = IO(new TrapHandleIO) 13 14 private val trapInfo = io.in.trapInfo 15 private val privState = io.in.privState 16 private val mstatus = io.in.mstatus 17 private val vsstatus = io.in.vsstatus 18 private val mnstatus = io.in.mnstatus 19 private val mideleg = io.in.mideleg.asUInt 20 private val hideleg = io.in.hideleg.asUInt 21 private val medeleg = io.in.medeleg.asUInt 22 private val hedeleg = io.in.hedeleg.asUInt 23 private val mvien = io.in.mvien.asUInt 24 private val hvien = io.in.hvien.asUInt 25 private val virtualInterruptIsHvictlInject = io.in.virtualInterruptIsHvictlInject 26 27 private val hasTrap = trapInfo.valid 28 private val hasNMI = hasTrap && trapInfo.bits.nmi 29 private val hasIR = hasTrap && trapInfo.bits.isInterrupt 30 private val hasEX = hasTrap && !trapInfo.bits.isInterrupt 31 32 private val exceptionVec = io.in.trapInfo.bits.trapVec 33 private val intrVec = io.in.trapInfo.bits.intrVec 34 private val hasEXVec = Mux(hasEX, exceptionVec, 0.U) 35 private val hasIRVec = Mux(hasIR, intrVec, 0.U) 36 37 private val highestPrioNMIVec = Wire(Vec(64, Bool())) 38 highestPrioNMIVec.zipWithIndex.foreach { case (irq, i) => 39 if (NonMaskableIRNO.interruptDefaultPrio.contains(i)) { 40 val higherIRSeq = NonMaskableIRNO.getIRQHigherThan(i) 41 irq := ( 42 higherIRSeq.nonEmpty.B && Cat(higherIRSeq.map(num => !hasIRVec(num))).andR || 43 higherIRSeq.isEmpty.B 44 ) && hasIRVec(i) 45 dontTouch(irq) 46 } else 47 irq := false.B 48 } 49 50 private val highestPrioEXVec = Wire(Vec(64, Bool())) 51 highestPrioEXVec.zipWithIndex.foreach { case (excp, i) => 52 if (ExceptionNO.priorities.contains(i)) { 53 val higherEXSeq = ExceptionNO.getHigherExcpThan(i) 54 excp := ( 55 higherEXSeq.nonEmpty.B && Cat(higherEXSeq.map(num => !hasEXVec(num))).andR || 56 higherEXSeq.isEmpty.B 57 ) && hasEXVec(i) 58 } else 59 excp := false.B 60 } 61 62 private val highestPrioIR = hasIRVec.asUInt 63 private val highestPrioNMI = highestPrioNMIVec.asUInt 64 private val highestPrioEX = highestPrioEXVec.asUInt 65 66 67 private val mIRVec = dontTouch(WireInit(highestPrioIR)) 68 private val hsIRVec = (mIRVec & mideleg) | (mIRVec & mvien & ~mideleg) 69 private val vsIRVec = (hsIRVec & hideleg) | (hsIRVec & hvien & ~hideleg) 70 71 private val mEXVec = highestPrioEX 72 private val hsEXVec = highestPrioEX & medeleg 73 private val vsEXVec = highestPrioEX & medeleg & hedeleg 74 75 // nmi handle in MMode only and default handler is mtvec 76 private val mHasIR = mIRVec.orR 77 private val hsHasIR = hsIRVec.orR & !hasNMI 78 private val vsHasIR = (vsIRVec.orR || hasIR && virtualInterruptIsHvictlInject) & !hasNMI 79 80 private val mHasEX = mEXVec.orR 81 private val hsHasEX = hsEXVec.orR 82 private val vsHasEX = vsEXVec.orR 83 84 private val mHasTrap = mHasEX || mHasIR 85 private val hsHasTrap = hsHasEX || hsHasIR 86 private val vsHasTrap = vsHasEX || vsHasIR 87 88 private val handleTrapUnderHS = !privState.isModeM && hsHasTrap 89 private val handleTrapUnderVS = privState.isVirtual && vsHasTrap 90 private val handleTrapUnderM = !handleTrapUnderVS && !handleTrapUnderHS 91 92 // Todo: support more interrupt and exception 93 private val exceptionRegular = OHToUInt(highestPrioEX) 94 private val interruptNO = OHToUInt(Mux(hasNMI, highestPrioNMI, highestPrioIR)) 95 private val exceptionNO = Mux(trapInfo.bits.singleStep, ExceptionNO.breakPoint.U, exceptionRegular) 96 97 private val causeNO = Mux(hasIR, interruptNO, exceptionNO) 98 99 // sm/ssdbltrp 100 private val m_EX_DT = handleTrapUnderM && mstatus.MDT.asBool && hasTrap 101 private val s_EX_DT = handleTrapUnderHS && mstatus.SDT.asBool && hasTrap 102 private val vs_EX_DT = handleTrapUnderVS && vsstatus.SDT.asBool && hasTrap 103 104 private val dbltrpToMN = m_EX_DT && mnstatus.NMIE.asBool // NMI not allow double trap 105 private val hasDTExcp = m_EX_DT || s_EX_DT || vs_EX_DT 106 107 private val trapToHS = handleTrapUnderHS && !s_EX_DT && !vs_EX_DT 108 private val traptoVS = handleTrapUnderVS && !vs_EX_DT 109 110 private val xtvec = MuxCase(io.in.mtvec, Seq( 111 traptoVS -> io.in.vstvec, 112 trapToHS -> io.in.stvec 113 )) 114 private val pcFromXtvec = Cat(xtvec.addr.asUInt + Mux(xtvec.mode === XtvecMode.Vectored && hasIR, interruptNO(5, 0), 0.U), 0.U(2.W)) 115 116 io.out.entryPrivState := MuxCase(default = PrivState.ModeM, mapping = Seq( 117 traptoVS -> PrivState.ModeVS, 118 trapToHS -> PrivState.ModeHS, 119 )) 120 121 io.out.causeNO.Interrupt := hasIR 122 io.out.causeNO.ExceptionCode := causeNO 123 io.out.pcFromXtvec := pcFromXtvec 124 io.out.hasDTExcp := hasDTExcp 125 io.out.dbltrpToMN := dbltrpToMN 126 127} 128 129class TrapHandleIO extends Bundle { 130 val in = Input(new Bundle { 131 val trapInfo = ValidIO(new Bundle { 132 val trapVec = UInt(64.W) 133 val nmi = Bool() 134 val intrVec = UInt(64.W) 135 val isInterrupt = Bool() 136 val singleStep = Bool() 137 }) 138 val privState = new PrivState 139 val mstatus = new MstatusBundle 140 val vsstatus = new SstatusBundle 141 val mnstatus = new MnstatusBundle 142 val mideleg = new MidelegBundle 143 val medeleg = new MedelegBundle 144 val hideleg = new HidelegBundle 145 val hedeleg = new HedelegBundle 146 val mvien = new MvienBundle 147 val hvien = new HvienBundle 148 // trap vector 149 val mtvec = Input(new XtvecBundle) 150 val stvec = Input(new XtvecBundle) 151 val vstvec = Input(new XtvecBundle) 152 // virtual interrupt is hvictl inject 153 val virtualInterruptIsHvictlInject = Input(Bool()) 154 }) 155 156 val out = new Bundle { 157 val entryPrivState = new PrivState 158 val causeNO = new CauseBundle 159 val dbltrpToMN = Bool() 160 val hasDTExcp = Bool() 161 val pcFromXtvec = UInt() 162 } 163}