1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).EnableDifftest 42 43 def basicDebugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || debugEn 44 45 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 46 47 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 48 copyPdestInfo.addOne(x) 49 } 50 def isCopyPdest(exuIdx: Int): Boolean = { 51 copyPdestInfo.contains(exuIdx) 52 } 53 def connectWakeup(exuIdx: Int): Unit = { 54 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 55 if (copyPdestInfo.contains(exuIdx)) { 56 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 57 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 58 copyPdestInfo.remove(exuIdx) 59 copyPdestInfo += newInfo 60 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 61 } 62 } 63 def getCopyPdestIndex(exuIdx: Int): Int = { 64 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 65 } 66 def intSchdParams = schdParams.get(IntScheduler()) 67 def fpSchdParams = schdParams.get(FpScheduler()) 68 def vfSchdParams = schdParams.get(VfScheduler()) 69 def memSchdParams = schdParams.get(MemScheduler()) 70 def allSchdParams: Seq[SchdBlockParams] = 71 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 72 .filter(_.nonEmpty) 73 .map(_.get) 74 def allIssueParams: Seq[IssueBlockParams] = 75 allSchdParams.map(_.issueBlockParams).flatten 76 def allExuParams: Seq[ExeUnitParams] = 77 allIssueParams.map(_.exuBlockParams).flatten 78 79 // filter not fake exu unit 80 def allRealExuParams = 81 allExuParams.filterNot(_.fakeUnit) 82 83 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 84 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 85 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 86 def v0PregParams: V0PregParams = pregParams.collectFirst { case x: V0PregParams => x }.get 87 def vlPregParams: VlPregParams = pregParams.collectFirst { case x: VlPregParams => x }.get 88 def getPregParams: Map[DataConfig, PregParams] = { 89 pregParams.map(x => (x.dataCfg, x)).toMap 90 } 91 92 def pregIdxWidth = pregParams.map(_.addrWidth).max 93 94 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 95 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 96 def numIntRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numIntSrc).max).max 97 def numFpRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numFpSrc).max).max 98 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 99 100 101 def AluCnt = allSchdParams.map(_.AluCnt).sum 102 def StaCnt = allSchdParams.map(_.StaCnt).sum 103 def StdCnt = allSchdParams.map(_.StdCnt).sum 104 def LduCnt = allSchdParams.map(_.LduCnt).sum 105 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 106 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 107 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 108 def LsExuCnt = StaCnt + LduCnt + HyuCnt 109 val LdExuCnt = LduCnt + HyuCnt 110 val StaExuCnt = StaCnt + HyuCnt 111 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 112 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 113 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 114 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 115 116 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 117 def numPcMemReadPort = allExuParams.filter(_.needPc).size 118 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 119 120 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 121 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 122 123 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 124 def numExu = allSchdParams.map(_.numExu).sum 125 126 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 127 128 def numRedirect = 1 // only for ahead info to frontend 129 130 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 131 132 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 133 134 def genIntIQValidNumBundle(implicit p: Parameters) = { 135 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 136 } 137 138 def genFpIQValidNumBundle(implicit p: Parameters) = { 139 this.fpSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 140 } 141 142 def genIntWriteBackBundle(implicit p: Parameters) = { 143 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 144 } 145 146 def genFpWriteBackBundle(implicit p: Parameters) = { 147 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 148 } 149 150 def genVfWriteBackBundle(implicit p: Parameters) = { 151 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 152 } 153 154 def genV0WriteBackBundle(implicit p: Parameters) = { 155 Seq.fill(this.getV0RfWriteSize)(new RfWritePortWithConfig(V0Data(), v0PregParams.addrWidth)) 156 } 157 158 def genVlWriteBackBundle(implicit p: Parameters) = { 159 Seq.fill(this.getVlRfWriteSize)(new RfWritePortWithConfig(VlData(), vlPregParams.addrWidth)) 160 } 161 162 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 163 genIntWriteBackBundle ++ genVfWriteBackBundle 164 } 165 166 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 167 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 168 } 169 170 def getIntWbArbiterParams: WbArbiterParams = { 171 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 172 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 173 } 174 175 def getVfWbArbiterParams: WbArbiterParams = { 176 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 177 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 178 } 179 180 def getFpWbArbiterParams: WbArbiterParams = { 181 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 182 datapath.WbArbiterParams(fpWbCfgs, vfPregParams, this) 183 } 184 185 def getV0WbArbiterParams: WbArbiterParams = { 186 val v0WbCfgs: Seq[V0WB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeV0)).map(_.asInstanceOf[V0WB]) 187 datapath.WbArbiterParams(v0WbCfgs, v0PregParams, this) 188 } 189 190 def getVlWbArbiterParams: WbArbiterParams = { 191 val vlWbCfgs: Seq[VlWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVl)).map(_.asInstanceOf[VlWB]) 192 datapath.WbArbiterParams(vlWbCfgs, vlPregParams, this) 193 } 194 195 /** 196 * Get regfile read port params 197 * 198 * @param dataCfg [[IntData]] or [[VecData]] 199 * @return Seq[port->Seq[(exuIdx, priority)] 200 */ 201 def getRdPortParams(dataCfg: DataConfig) = { 202 // port -> Seq[exuIdx, priority] 203 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 204 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 205 .filter { x => x._1.getDataConfig == dataCfg } 206 .map(x => (x._1.port, (x._2, x._1.priority))) 207 .groupBy(_._1) 208 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 209 .toSeq 210 .sortBy(_._1) 211 cfgs 212 } 213 214 /** 215 * Get regfile write back port params 216 * 217 * @param dataCfg [[IntData]] or [[VecData]] 218 * @return Seq[port->Seq[(exuIdx, priority)] 219 */ 220 def getWbPortParams(dataCfg: DataConfig) = { 221 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 222 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 223 .filter { x => x._1.dataCfg == dataCfg } 224 .map(x => (x._1.port, (x._2, x._1.priority))) 225 .groupBy(_._1) 226 .map(x => (x._1, x._2.map(_._2))) 227 .toSeq 228 .sortBy(_._1) 229 cfgs 230 } 231 232 def getRdPortIndices(dataCfg: DataConfig) = { 233 this.getRdPortParams(dataCfg).map(_._1) 234 } 235 236 def getWbPortIndices(dataCfg: DataConfig) = { 237 this.getWbPortParams(dataCfg).map(_._1) 238 } 239 240 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 241 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 242 _.exuBlockParams.map( 243 _.rfrPortConfigs.map( 244 _.collectFirst{ case x: T => x } 245 .getOrElse(NoRD()) 246 ) 247 ) 248 ) 249 rdCfgs 250 } 251 252 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 253 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 254 } 255 256 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 257 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 258 wbCfgs 259 } 260 261 /** 262 * Get size of read ports of int regfile 263 * 264 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 265 */ 266 def getIntRfReadSize = { 267 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 268 } 269 270 /** 271 * Get size of write ports of int regfile 272 * 273 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 274 */ 275 def getIntRfWriteSize = { 276 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 277 } 278 279 /** 280 * Get size of write ports of fp regfile 281 * 282 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 283 */ 284 def getFpRfWriteSize = { 285 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 286 } 287 288 /** 289 * Get size of read ports of vec regfile 290 * 291 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 292 */ 293 def getVfRfReadSize = { 294 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 295 } 296 297 /** 298 * Get size of write ports of vec regfile 299 * 300 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 301 */ 302 def getVfRfWriteSize = { 303 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 304 } 305 306 def getV0RfWriteSize = { 307 this.v0PregParams.numWrite.getOrElse(this.getWbPortIndices(V0Data()).size) 308 } 309 310 def getVlRfWriteSize = { 311 this.vlPregParams.numWrite.getOrElse(this.getWbPortIndices(VlData()).size) 312 } 313 314 def getRfReadSize(dataCfg: DataConfig) = { 315 dataCfg match{ 316 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 317 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 318 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 319 case V0Data() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 320 case VlData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 321 case _ => throw new IllegalArgumentException(s"DataConfig ${dataCfg} can not get RfReadSize") 322 } 323 } 324 325 def getRfWriteSize(dataCfg: DataConfig) = { 326 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 327 } 328 329 330 /** 331 * Get size of read ports of int regcache 332 */ 333 def getIntExuRCReadSize = { 334 this.allExuParams.filter(x => x.isIntExeUnit).map(_.numIntSrc).reduce(_ + _) 335 } 336 337 def getMemExuRCReadSize = { 338 this.allExuParams.filter(x => x.isMemExeUnit && x.readIntRf).map(_.numIntSrc).reduce(_ + _) 339 } 340 341 /** 342 * Get size of write ports of int regcache 343 */ 344 def getIntExuRCWriteSize = { 345 this.allExuParams.filter(x => x.isIntExeUnit && x.isIQWakeUpSource).size 346 } 347 348 def getMemExuRCWriteSize = { 349 this.allExuParams.filter(x => x.isMemExeUnit && x.isIQWakeUpSource && x.readIntRf).size 350 } 351 352 def getExuIdx(name: String): Int = { 353 val exuParams = allRealExuParams 354 if (name != "WB") { 355 val foundExu = exuParams.find(_.name == name) 356 require(foundExu.nonEmpty, s"exu $name not find") 357 foundExu.get.exuIdx 358 } else 359 -1 360 } 361 362 def getExuName(idx: Int): String = { 363 val exuParams = allRealExuParams 364 exuParams(idx).name 365 } 366 367 def getExuParamByName(name: String): ExeUnitParams = { 368 val exuParams = allExuParams 369 exuParams.find(_.name == name).get 370 } 371 372 def getLdExuIdx(exu: ExeUnitParams): Int = { 373 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 374 ldExuParams.indexOf(exu) 375 } 376 377 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 378 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 379 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 380 def getV0WBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 381 def getVlWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 382 383 private def isContinuous(portIndices: Seq[Int]): Boolean = { 384 val portIndicesSet = portIndices.toSet 385 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 386 } 387 388 def configChecks = { 389 checkReadPortContinuous 390 checkWritePortContinuous 391 configCheck 392 } 393 394 def checkReadPortContinuous = { 395 pregParams.filterNot(_.isFake).foreach { x => 396 if (x.numRead.isEmpty) { 397 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 398 require(isContinuous(portIndices), 399 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 400 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 401 } 402 } 403 } 404 405 def checkWritePortContinuous = { 406 pregParams.filterNot(_.isFake).foreach { x => 407 if (x.numWrite.isEmpty) { 408 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 409 require( 410 isContinuous(portIndices), 411 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 412 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 413 ) 414 } 415 } 416 } 417 418 def configCheck = { 419 // check 0 420 val maxPortSource = 4 421 422 allRealExuParams.map { 423 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 424 }.filter(_.isDefined).groupBy(_.get.port).foreach { 425 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 426 } 427 allRealExuParams.map { 428 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 429 }.filter(_.isDefined).groupBy(_.get.port).foreach { 430 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 431 } 432 433 // check 1 434 // if some exus share the same wb port and rd ports, 435 // the exu with high priority at wb must also have high priority at rd. 436 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 437 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 438 for(wbType <- wbTypes){ 439 for(rdType <- rdTypes){ 440 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 441 allRealExuParams.map { 442 case exuParam => 443 val wbPortConfigs = exuParam.wbPortConfigs 444 val wbConfigs = wbType match{ 445 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 446 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 447 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 448 case _ => None 449 } 450 val rfReadPortConfigs = exuParam.rfrPortConfigs 451 val rdConfigs = rdType match{ 452 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 453 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 454 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 455 case _ => Seq() 456 } 457 (wbConfigs, rdConfigs) 458 }.filter(_._1.isDefined) 459 .sortBy(_._1.get.priority) 460 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 461 val rdCfgs = intWbRdPairs.map(_._2).flatten 462 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 463 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 464 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 465 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 466 } 467 } 468 } 469 } 470 } 471} 472