1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).EnableDifftest 42 43 def basicDebugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || debugEn 44 45 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 46 47 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 48 copyPdestInfo.addOne(x) 49 } 50 def isCopyPdest(exuIdx: Int): Boolean = { 51 copyPdestInfo.contains(exuIdx) 52 } 53 def connectWakeup(exuIdx: Int): Unit = { 54 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 55 if (copyPdestInfo.contains(exuIdx)) { 56 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 57 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 58 copyPdestInfo.remove(exuIdx) 59 copyPdestInfo += newInfo 60 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 61 } 62 } 63 def getCopyPdestIndex(exuIdx: Int): Int = { 64 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 65 } 66 def intSchdParams = schdParams.get(IntScheduler()) 67 def fpSchdParams = schdParams.get(FpScheduler()) 68 def vfSchdParams = schdParams.get(VfScheduler()) 69 def memSchdParams = schdParams.get(MemScheduler()) 70 def allSchdParams: Seq[SchdBlockParams] = 71 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 72 .filter(_.nonEmpty) 73 .map(_.get) 74 def allIssueParams: Seq[IssueBlockParams] = 75 allSchdParams.map(_.issueBlockParams).flatten 76 def allExuParams: Seq[ExeUnitParams] = 77 allIssueParams.map(_.exuBlockParams).flatten 78 79 // filter not fake exu unit 80 def allRealExuParams = 81 allExuParams.filterNot(_.fakeUnit) 82 83 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 84 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 85 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 86 def v0PregParams: V0PregParams = pregParams.collectFirst { case x: V0PregParams => x }.get 87 def vlPregParams: VlPregParams = pregParams.collectFirst { case x: VlPregParams => x }.get 88 def getPregParams: Map[DataConfig, PregParams] = { 89 pregParams.map(x => (x.dataCfg, x)).toMap 90 } 91 92 def pregIdxWidth = pregParams.map(_.addrWidth).max 93 94 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 95 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 96 def numIntRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numIntSrc).max).max 97 def numFpRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numFpSrc).max).max 98 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 99 100 101 def AluCnt = allSchdParams.map(_.AluCnt).sum 102 def StaCnt = allSchdParams.map(_.StaCnt).sum 103 def StdCnt = allSchdParams.map(_.StdCnt).sum 104 def LduCnt = allSchdParams.map(_.LduCnt).sum 105 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 106 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 107 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 108 def LsExuCnt = StaCnt + LduCnt + HyuCnt 109 val LdExuCnt = LduCnt + HyuCnt 110 val StaExuCnt = StaCnt + HyuCnt 111 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 112 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 113 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 114 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 115 116 def numPcMemReadPort = allExuParams.filter(_.needPc).size 117 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 118 119 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 120 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 121 122 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 123 def numExu = allSchdParams.map(_.numExu).sum 124 125 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 126 127 def numRedirect = 1 // only for ahead info to frontend 128 129 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 130 131 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 132 133 def genIntIQValidNumBundle(implicit p: Parameters) = { 134 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 135 } 136 137 def genFpIQValidNumBundle(implicit p: Parameters) = { 138 this.fpSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 139 } 140 141 def genIntWriteBackBundle(implicit p: Parameters) = { 142 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 143 } 144 145 def genFpWriteBackBundle(implicit p: Parameters) = { 146 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 147 } 148 149 def genVfWriteBackBundle(implicit p: Parameters) = { 150 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 151 } 152 153 def genV0WriteBackBundle(implicit p: Parameters) = { 154 Seq.fill(this.getV0RfWriteSize)(new RfWritePortWithConfig(V0Data(), v0PregParams.addrWidth)) 155 } 156 157 def genVlWriteBackBundle(implicit p: Parameters) = { 158 Seq.fill(this.getVlRfWriteSize)(new RfWritePortWithConfig(VlData(), vlPregParams.addrWidth)) 159 } 160 161 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 162 genIntWriteBackBundle ++ genVfWriteBackBundle 163 } 164 165 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 166 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 167 } 168 169 def getIntWbArbiterParams: WbArbiterParams = { 170 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 171 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 172 } 173 174 def getVfWbArbiterParams: WbArbiterParams = { 175 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 176 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 177 } 178 179 def getFpWbArbiterParams: WbArbiterParams = { 180 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 181 datapath.WbArbiterParams(fpWbCfgs, fpPregParams, this) 182 } 183 184 def getV0WbArbiterParams: WbArbiterParams = { 185 val v0WbCfgs: Seq[V0WB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeV0)).map(_.asInstanceOf[V0WB]) 186 datapath.WbArbiterParams(v0WbCfgs, v0PregParams, this) 187 } 188 189 def getVlWbArbiterParams: WbArbiterParams = { 190 val vlWbCfgs: Seq[VlWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVl)).map(_.asInstanceOf[VlWB]) 191 datapath.WbArbiterParams(vlWbCfgs, vlPregParams, this) 192 } 193 194 /** 195 * Get regfile read port params 196 * 197 * @param dataCfg [[IntData]] or [[VecData]] 198 * @return Seq[port->Seq[(exuIdx, priority)] 199 */ 200 def getRdPortParams(dataCfg: DataConfig) = { 201 // port -> Seq[exuIdx, priority] 202 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 203 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 204 .filter { x => x._1.getDataConfig == dataCfg } 205 .map(x => (x._1.port, (x._2, x._1.priority))) 206 .groupBy(_._1) 207 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 208 .toSeq 209 .sortBy(_._1) 210 cfgs 211 } 212 213 /** 214 * Get regfile write back port params 215 * 216 * @param dataCfg [[IntData]] or [[VecData]] 217 * @return Seq[port->Seq[(exuIdx, priority)] 218 */ 219 def getWbPortParams(dataCfg: DataConfig) = { 220 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 221 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 222 .filter { x => x._1.dataCfg == dataCfg } 223 .map(x => (x._1.port, (x._2, x._1.priority))) 224 .groupBy(_._1) 225 .map(x => (x._1, x._2.map(_._2))) 226 .toSeq 227 .sortBy(_._1) 228 cfgs 229 } 230 231 def getRdPortIndices(dataCfg: DataConfig) = { 232 this.getRdPortParams(dataCfg).map(_._1) 233 } 234 235 def getWbPortIndices(dataCfg: DataConfig) = { 236 this.getWbPortParams(dataCfg).map(_._1) 237 } 238 239 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 240 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 241 _.exuBlockParams.map( 242 _.rfrPortConfigs.map( 243 _.collectFirst{ case x: T => x } 244 .getOrElse(NoRD()) 245 ) 246 ) 247 ) 248 rdCfgs 249 } 250 251 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 252 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 253 } 254 255 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 256 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 257 wbCfgs 258 } 259 260 /** 261 * Get size of read ports of int regfile 262 * 263 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 264 */ 265 def getIntRfReadSize = { 266 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 267 } 268 269 /** 270 * Get size of write ports of int regfile 271 * 272 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 273 */ 274 def getIntRfWriteSize = { 275 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 276 } 277 278 /** 279 * Get size of write ports of fp regfile 280 * 281 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 282 */ 283 def getFpRfWriteSize = { 284 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 285 } 286 287 /** 288 * Get size of read ports of vec regfile 289 * 290 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 291 */ 292 def getVfRfReadSize = { 293 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 294 } 295 296 /** 297 * Get size of write ports of vec regfile 298 * 299 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 300 */ 301 def getVfRfWriteSize = { 302 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 303 } 304 305 def getV0RfWriteSize = { 306 this.v0PregParams.numWrite.getOrElse(this.getWbPortIndices(V0Data()).size) 307 } 308 309 def getVlRfWriteSize = { 310 this.vlPregParams.numWrite.getOrElse(this.getWbPortIndices(VlData()).size) 311 } 312 313 def getRfReadSize(dataCfg: DataConfig) = { 314 dataCfg match{ 315 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 316 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 317 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 318 case V0Data() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 319 case VlData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 320 case _ => throw new IllegalArgumentException(s"DataConfig ${dataCfg} can not get RfReadSize") 321 } 322 } 323 324 def getRfWriteSize(dataCfg: DataConfig) = { 325 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 326 } 327 328 329 /** 330 * Get size of read ports of int regcache 331 */ 332 def getIntExuRCReadSize = { 333 this.allExuParams.filter(x => x.isIntExeUnit).map(_.numIntSrc).reduce(_ + _) 334 } 335 336 def getMemExuRCReadSize = { 337 this.allExuParams.filter(x => x.isMemExeUnit && x.readIntRf).map(_.numIntSrc).reduce(_ + _) 338 } 339 340 /** 341 * Get size of write ports of int regcache 342 */ 343 def getIntExuRCWriteSize = { 344 this.allExuParams.filter(x => x.isIntExeUnit && x.isIQWakeUpSource).size 345 } 346 347 def getMemExuRCWriteSize = { 348 this.allExuParams.filter(x => x.isMemExeUnit && x.isIQWakeUpSource && x.readIntRf).size 349 } 350 351 def getExuIdx(name: String): Int = { 352 val exuParams = allRealExuParams 353 if (name != "WB") { 354 val foundExu = exuParams.find(_.name == name) 355 require(foundExu.nonEmpty, s"exu $name not find") 356 foundExu.get.exuIdx 357 } else 358 -1 359 } 360 361 def getExuName(idx: Int): String = { 362 val exuParams = allRealExuParams 363 exuParams(idx).name 364 } 365 366 def getExuParamByName(name: String): ExeUnitParams = { 367 val exuParams = allExuParams 368 exuParams.find(_.name == name).get 369 } 370 371 def getLdExuIdx(exu: ExeUnitParams): Int = { 372 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 373 ldExuParams.indexOf(exu) 374 } 375 376 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 377 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 378 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 379 def getV0WBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 380 def getVlWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 381 382 private def isContinuous(portIndices: Seq[Int]): Boolean = { 383 val portIndicesSet = portIndices.toSet 384 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 385 } 386 387 def configChecks = { 388 checkReadPortContinuous 389 checkWritePortContinuous 390 configCheck 391 } 392 393 def checkReadPortContinuous = { 394 pregParams.filterNot(_.isFake).foreach { x => 395 if (x.numRead.isEmpty) { 396 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 397 require(isContinuous(portIndices), 398 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 399 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 400 } 401 } 402 } 403 404 def checkWritePortContinuous = { 405 pregParams.filterNot(_.isFake).foreach { x => 406 if (x.numWrite.isEmpty) { 407 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 408 require( 409 isContinuous(portIndices), 410 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 411 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 412 ) 413 } 414 } 415 } 416 417 def configCheck = { 418 // check 0 419 val maxPortSource = 4 420 421 allRealExuParams.map { 422 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 423 }.filter(_.isDefined).groupBy(_.get.port).foreach { 424 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 425 } 426 allRealExuParams.map { 427 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 428 }.filter(_.isDefined).groupBy(_.get.port).foreach { 429 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 430 } 431 432 // check 1 433 // if some exus share the same wb port and rd ports, 434 // the exu with high priority at wb must also have high priority at rd. 435 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 436 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 437 for(wbType <- wbTypes){ 438 for(rdType <- rdTypes){ 439 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 440 allRealExuParams.map { 441 case exuParam => 442 val wbPortConfigs = exuParam.wbPortConfigs 443 val wbConfigs = wbType match{ 444 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 445 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 446 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 447 case _ => None 448 } 449 val rfReadPortConfigs = exuParam.rfrPortConfigs 450 val rdConfigs = rdType match{ 451 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 452 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 453 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 454 case _ => Seq() 455 } 456 (wbConfigs, rdConfigs) 457 }.filter(_._1.isDefined) 458 .sortBy(_._1.get.priority) 459 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 460 val rdCfgs = intWbRdPairs.map(_._2).flatten 461 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 462 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 463 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 464 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 465 } 466 } 467 } 468 } 469 } 470} 471