History log of /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala (Results 1 – 25 of 52)
Revision Date Author Comments
# 914bbc86 20-Feb-2025 xiaofeibao-xjtu <[email protected]>

chore(dispatch): remove useless code and files (#4288)


# b8377868 27-Jan-2025 Zihao Yu <[email protected]>

fix(backend, BackendParams): fix wrong PregParams (#4225)


# f7fe02a8 30-Dec-2024 junxiong-ji <[email protected]>

style(decode): add comments and small modification on code style (#3774)


# 63d67ef3 14-Sep-2024 Tang Haojin <[email protected]>

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

show more ...


# 955b4bea 22-Jul-2024 sinsanction <[email protected]>

Scheduler, RegCache: add RegCacheTagTable to read reg cache state before entering issue queue


# ae4984bf 28-Jun-2024 sinsanction <[email protected]>

Parameters: add parameters for reg cache


# 54c6d89d 24-Jul-2024 xiaofeibao-xjtu <[email protected]>

Redirect fix timing (#3209)


# 45d40ce7 30-May-2024 sinsanction <[email protected]>

WbDataPath: support v0 & vl split


# e4e52e7d 29-May-2024 sinsanction <[email protected]>

DataPath: support v0 & vl split


# 07b5cc60 29-May-2024 xiaofeibao <[email protected]>

Backend: change MaskSrcData VConfigData to V0Data VlData


# de8bd1d0 28-May-2024 sinsanction <[email protected]>

Backend: update all Params' signals and methods for v0 & vl split


# 2aa3a761 27-May-2024 sinsanction <[email protected]>

Backend: add some basic signals for v0 & vl split


# 82674533 15-May-2024 xiaofeibao <[email protected]>

Backend: add Dispatch2IqFpImp


# 60f0c5ae 26-Apr-2024 xiaofeibao <[email protected]>

Backend: add FpScheduler


# 8d035b8d 10-Apr-2024 sinsanction <[email protected]>

BackendParams: more readable port config check


# f4b98c41 20-Mar-2024 sinsanction <[email protected]>

Parameters: fix the count of vector read ports


# 81535d7b 15-Mar-2024 sinsanction <[email protected]>

Backend: remove unused extra RF read ports, connect real commit vtype to VTypeGen


# 6ccce570 14-Mar-2024 zhanglyGit <[email protected]>

Backend: rm one brh fu and modify Dispatch to adpot to it


# 5edcc45f 08-Mar-2024 Haojin Tang <[email protected]>

Parameters: remove write port configs for store


# c1e19666 04-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: implement uncertain latency exeUnit WbArbiter


# 5f80df32 15-Dec-2023 xiaofeibao-xjtu <[email protected]>

IQ: remove unused pc and ftqptr


# 4c5a0d77 06-Dec-2023 xiaofeibao-xjtu <[email protected]>

WakeupQueue: Copy all bits


# 0c7ebb58 04-Dec-2023 xiaofeibao-xjtu <[email protected]>

WakeupQueue: pdest copy


# d97a1af7 08-Jan-2024 Xuan Hu <[email protected]>

Backend,MemBlock,params: expand the width of enq of LSQ


# 46908ecf 06-Nov-2023 Xuan Hu <[email protected]>

backend,param: merge vldu and vstu into one exu


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