1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 42 43 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 44 45 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 46 copyPdestInfo.addOne(x) 47 } 48 def isCopyPdest(exuIdx: Int): Boolean = { 49 copyPdestInfo.contains(exuIdx) 50 } 51 def connectWakeup(exuIdx: Int): Unit = { 52 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 53 if (copyPdestInfo.contains(exuIdx)) { 54 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 55 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 56 copyPdestInfo.remove(exuIdx) 57 copyPdestInfo += newInfo 58 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 59 } 60 } 61 def getCopyPdestIndex(exuIdx: Int): Int = { 62 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 63 } 64 def intSchdParams = schdParams.get(IntScheduler()) 65 def fpSchdParams = schdParams.get(FpScheduler()) 66 def vfSchdParams = schdParams.get(VfScheduler()) 67 def memSchdParams = schdParams.get(MemScheduler()) 68 def allSchdParams: Seq[SchdBlockParams] = 69 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 70 .filter(_.nonEmpty) 71 .map(_.get) 72 def allIssueParams: Seq[IssueBlockParams] = 73 allSchdParams.map(_.issueBlockParams).flatten 74 def allExuParams: Seq[ExeUnitParams] = 75 allIssueParams.map(_.exuBlockParams).flatten 76 77 // filter not fake exu unit 78 def allRealExuParams = 79 allExuParams.filterNot(_.fakeUnit) 80 81 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 82 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def v0PregParams: V0PregParams = pregParams.collectFirst { case x: V0PregParams => x }.get 85 def vlPregParams: VlPregParams = pregParams.collectFirst { case x: VlPregParams => x }.get 86 def getPregParams: Map[DataConfig, PregParams] = { 87 pregParams.map(x => (x.dataCfg, x)).toMap 88 } 89 90 def pregIdxWidth = pregParams.map(_.addrWidth).max 91 92 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 93 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 94 def numIntRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numIntSrc).max).max 95 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 96 97 98 def AluCnt = allSchdParams.map(_.AluCnt).sum 99 def StaCnt = allSchdParams.map(_.StaCnt).sum 100 def StdCnt = allSchdParams.map(_.StdCnt).sum 101 def LduCnt = allSchdParams.map(_.LduCnt).sum 102 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 103 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 104 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 105 def LsExuCnt = StaCnt + LduCnt + HyuCnt 106 val LdExuCnt = LduCnt + HyuCnt 107 val StaExuCnt = StaCnt + HyuCnt 108 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 109 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 110 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 111 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 112 113 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 114 def numPcMemReadPort = allExuParams.filter(_.needPc).size 115 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 116 117 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 118 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 119 120 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 121 def numExu = allSchdParams.map(_.numExu).sum 122 123 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 124 125 def numRedirect = 1 // only for ahead info to frontend 126 127 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 128 129 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 130 131 def genIntIQValidNumBundle(implicit p: Parameters) = { 132 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 133 } 134 135 def genFpIQValidNumBundle(implicit p: Parameters) = { 136 this.fpSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 137 } 138 139 def genIntWriteBackBundle(implicit p: Parameters) = { 140 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 141 } 142 143 def genFpWriteBackBundle(implicit p: Parameters) = { 144 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 145 } 146 147 def genVfWriteBackBundle(implicit p: Parameters) = { 148 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 149 } 150 151 def genV0WriteBackBundle(implicit p: Parameters) = { 152 Seq.fill(this.getV0RfWriteSize)(new RfWritePortWithConfig(V0Data(), v0PregParams.addrWidth)) 153 } 154 155 def genVlWriteBackBundle(implicit p: Parameters) = { 156 Seq.fill(this.getVlRfWriteSize)(new RfWritePortWithConfig(VlData(), vlPregParams.addrWidth)) 157 } 158 159 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 160 genIntWriteBackBundle ++ genVfWriteBackBundle 161 } 162 163 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 164 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 165 } 166 167 def getIntWbArbiterParams: WbArbiterParams = { 168 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 169 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 170 } 171 172 def getVfWbArbiterParams: WbArbiterParams = { 173 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 174 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 175 } 176 177 def getFpWbArbiterParams: WbArbiterParams = { 178 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 179 datapath.WbArbiterParams(fpWbCfgs, vfPregParams, this) 180 } 181 182 def getV0WbArbiterParams: WbArbiterParams = { 183 val v0WbCfgs: Seq[V0WB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeV0)).map(_.asInstanceOf[V0WB]) 184 datapath.WbArbiterParams(v0WbCfgs, v0PregParams, this) 185 } 186 187 def getVlWbArbiterParams: WbArbiterParams = { 188 val vlWbCfgs: Seq[VlWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVl)).map(_.asInstanceOf[VlWB]) 189 datapath.WbArbiterParams(vlWbCfgs, vlPregParams, this) 190 } 191 192 /** 193 * Get regfile read port params 194 * 195 * @param dataCfg [[IntData]] or [[VecData]] 196 * @return Seq[port->Seq[(exuIdx, priority)] 197 */ 198 def getRdPortParams(dataCfg: DataConfig) = { 199 // port -> Seq[exuIdx, priority] 200 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 201 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 202 .filter { x => x._1.getDataConfig == dataCfg } 203 .map(x => (x._1.port, (x._2, x._1.priority))) 204 .groupBy(_._1) 205 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 206 .toSeq 207 .sortBy(_._1) 208 cfgs 209 } 210 211 /** 212 * Get regfile write back port params 213 * 214 * @param dataCfg [[IntData]] or [[VecData]] 215 * @return Seq[port->Seq[(exuIdx, priority)] 216 */ 217 def getWbPortParams(dataCfg: DataConfig) = { 218 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 219 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 220 .filter { x => x._1.dataCfg == dataCfg } 221 .map(x => (x._1.port, (x._2, x._1.priority))) 222 .groupBy(_._1) 223 .map(x => (x._1, x._2.map(_._2))) 224 .toSeq 225 .sortBy(_._1) 226 cfgs 227 } 228 229 def getRdPortIndices(dataCfg: DataConfig) = { 230 this.getRdPortParams(dataCfg).map(_._1) 231 } 232 233 def getWbPortIndices(dataCfg: DataConfig) = { 234 this.getWbPortParams(dataCfg).map(_._1) 235 } 236 237 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 238 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 239 _.exuBlockParams.map( 240 _.rfrPortConfigs.map( 241 _.collectFirst{ case x: T => x } 242 .getOrElse(NoRD()) 243 ) 244 ) 245 ) 246 rdCfgs 247 } 248 249 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 250 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 251 } 252 253 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 254 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 255 wbCfgs 256 } 257 258 /** 259 * Get size of read ports of int regfile 260 * 261 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 262 */ 263 def getIntRfReadSize = { 264 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 265 } 266 267 /** 268 * Get size of write ports of int regfile 269 * 270 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 271 */ 272 def getIntRfWriteSize = { 273 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 274 } 275 276 /** 277 * Get size of write ports of fp regfile 278 * 279 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 280 */ 281 def getFpRfWriteSize = { 282 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 283 } 284 285 /** 286 * Get size of read ports of vec regfile 287 * 288 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 289 */ 290 def getVfRfReadSize = { 291 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 292 } 293 294 /** 295 * Get size of write ports of vec regfile 296 * 297 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 298 */ 299 def getVfRfWriteSize = { 300 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 301 } 302 303 def getV0RfWriteSize = { 304 this.v0PregParams.numWrite.getOrElse(this.getWbPortIndices(V0Data()).size) 305 } 306 307 def getVlRfWriteSize = { 308 this.vlPregParams.numWrite.getOrElse(this.getWbPortIndices(VlData()).size) 309 } 310 311 def getRfReadSize(dataCfg: DataConfig) = { 312 dataCfg match{ 313 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 314 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 315 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 316 case V0Data() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 317 case VlData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 318 case _ => throw new IllegalArgumentException(s"DataConfig ${dataCfg} can not get RfReadSize") 319 } 320 } 321 322 def getRfWriteSize(dataCfg: DataConfig) = { 323 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 324 } 325 326 327 /** 328 * Get size of read ports of int regcache 329 */ 330 def getIntExuRCReadSize = { 331 this.allExuParams.filter(x => x.isIntExeUnit).map(_.numIntSrc).reduce(_ + _) 332 } 333 334 def getMemExuRCReadSize = { 335 this.allExuParams.filter(x => x.isMemExeUnit && x.readIntRf).map(_.numIntSrc).reduce(_ + _) 336 } 337 338 /** 339 * Get size of write ports of int regcache 340 */ 341 def getIntExuRCWriteSize = { 342 this.allExuParams.filter(x => x.isIntExeUnit && x.isIQWakeUpSource).size 343 } 344 345 def getMemExuRCWriteSize = { 346 this.allExuParams.filter(x => x.isMemExeUnit && x.isIQWakeUpSource && x.readIntRf).size 347 } 348 349 def getExuIdx(name: String): Int = { 350 val exuParams = allRealExuParams 351 if (name != "WB") { 352 val foundExu = exuParams.find(_.name == name) 353 require(foundExu.nonEmpty, s"exu $name not find") 354 foundExu.get.exuIdx 355 } else 356 -1 357 } 358 359 def getExuName(idx: Int): String = { 360 val exuParams = allRealExuParams 361 exuParams(idx).name 362 } 363 364 def getExuParamByName(name: String): ExeUnitParams = { 365 val exuParams = allExuParams 366 exuParams.find(_.name == name).get 367 } 368 369 def getLdExuIdx(exu: ExeUnitParams): Int = { 370 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 371 ldExuParams.indexOf(exu) 372 } 373 374 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 375 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 376 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 377 def getV0WBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 378 def getVlWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 379 380 private def isContinuous(portIndices: Seq[Int]): Boolean = { 381 val portIndicesSet = portIndices.toSet 382 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 383 } 384 385 def configChecks = { 386 checkReadPortContinuous 387 checkWritePortContinuous 388 configCheck 389 } 390 391 def checkReadPortContinuous = { 392 pregParams.filterNot(_.isFake).foreach { x => 393 if (x.numRead.isEmpty) { 394 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 395 require(isContinuous(portIndices), 396 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 397 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 398 } 399 } 400 } 401 402 def checkWritePortContinuous = { 403 pregParams.filterNot(_.isFake).foreach { x => 404 if (x.numWrite.isEmpty) { 405 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 406 require( 407 isContinuous(portIndices), 408 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 409 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 410 ) 411 } 412 } 413 } 414 415 def configCheck = { 416 // check 0 417 val maxPortSource = 4 418 419 allRealExuParams.map { 420 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 421 }.filter(_.isDefined).groupBy(_.get.port).foreach { 422 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 423 } 424 allRealExuParams.map { 425 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 426 }.filter(_.isDefined).groupBy(_.get.port).foreach { 427 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 428 } 429 430 // check 1 431 // if some exus share the same wb port and rd ports, 432 // the exu with high priority at wb must also have high priority at rd. 433 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 434 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 435 for(wbType <- wbTypes){ 436 for(rdType <- rdTypes){ 437 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 438 allRealExuParams.map { 439 case exuParam => 440 val wbPortConfigs = exuParam.wbPortConfigs 441 val wbConfigs = wbType match{ 442 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 443 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 444 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 445 case _ => None 446 } 447 val rfReadPortConfigs = exuParam.rfrPortConfigs 448 val rdConfigs = rdType match{ 449 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 450 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 451 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 452 case _ => Seq() 453 } 454 (wbConfigs, rdConfigs) 455 }.filter(_._1.isDefined) 456 .sortBy(_._1.get.priority) 457 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 458 val rdCfgs = intWbRdPairs.map(_._2).flatten 459 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 460 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 461 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 462 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 463 } 464 } 465 } 466 } 467 } 468} 469