1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 42 43 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 44 45 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 46 copyPdestInfo.addOne(x) 47 } 48 def isCopyPdest(exuIdx: Int): Boolean = { 49 copyPdestInfo.contains(exuIdx) 50 } 51 def connectWakeup(exuIdx: Int): Unit = { 52 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 53 if (copyPdestInfo.contains(exuIdx)) { 54 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 55 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 56 copyPdestInfo.remove(exuIdx) 57 copyPdestInfo += newInfo 58 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 59 } 60 } 61 def getCopyPdestIndex(exuIdx: Int): Int = { 62 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 63 } 64 def intSchdParams = schdParams.get(IntScheduler()) 65 def fpSchdParams = schdParams.get(FpScheduler()) 66 def vfSchdParams = schdParams.get(VfScheduler()) 67 def memSchdParams = schdParams.get(MemScheduler()) 68 def allSchdParams: Seq[SchdBlockParams] = 69 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 70 .filter(_.nonEmpty) 71 .map(_.get) 72 def allIssueParams: Seq[IssueBlockParams] = 73 allSchdParams.map(_.issueBlockParams).flatten 74 def allExuParams: Seq[ExeUnitParams] = 75 allIssueParams.map(_.exuBlockParams).flatten 76 77 // filter not fake exu unit 78 def allRealExuParams = 79 allExuParams.filterNot(_.fakeUnit) 80 81 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 82 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def v0PregParams: V0PregParams = pregParams.collectFirst { case x: V0PregParams => x }.get 85 def vlPregParams: VlPregParams = pregParams.collectFirst { case x: VlPregParams => x }.get 86 def getPregParams: Map[DataConfig, PregParams] = { 87 pregParams.map(x => (x.dataCfg, x)).toMap 88 } 89 90 def pregIdxWidth = pregParams.map(_.addrWidth).max 91 92 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 93 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 94 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 95 96 97 def AluCnt = allSchdParams.map(_.AluCnt).sum 98 def StaCnt = allSchdParams.map(_.StaCnt).sum 99 def StdCnt = allSchdParams.map(_.StdCnt).sum 100 def LduCnt = allSchdParams.map(_.LduCnt).sum 101 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 102 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 103 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 104 def LsExuCnt = StaCnt + LduCnt + HyuCnt 105 val LdExuCnt = LduCnt + HyuCnt 106 val StaExuCnt = StaCnt + HyuCnt 107 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 108 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 109 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 110 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 111 112 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 113 def numPcMemReadPort = allExuParams.filter(_.needPc).size 114 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 115 116 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 117 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 118 119 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 120 def numExu = allSchdParams.map(_.numExu).sum 121 122 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 123 124 def numRedirect = allSchdParams.map(_.numRedirect).sum 125 126 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 127 128 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 129 130 def genIntIQValidNumBundle(implicit p: Parameters) = { 131 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 132 } 133 134 def genFpIQValidNumBundle(implicit p: Parameters) = { 135 this.fpSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 136 } 137 138 def genIntWriteBackBundle(implicit p: Parameters) = { 139 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 140 } 141 142 def genFpWriteBackBundle(implicit p: Parameters) = { 143 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 144 } 145 146 def genVfWriteBackBundle(implicit p: Parameters) = { 147 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 148 } 149 150 def genV0WriteBackBundle(implicit p: Parameters) = { 151 Seq.fill(this.getV0RfWriteSize)(new RfWritePortWithConfig(V0Data(), v0PregParams.addrWidth)) 152 } 153 154 def genVlWriteBackBundle(implicit p: Parameters) = { 155 Seq.fill(this.getVlRfWriteSize)(new RfWritePortWithConfig(VlData(), vlPregParams.addrWidth)) 156 } 157 158 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 159 genIntWriteBackBundle ++ genVfWriteBackBundle 160 } 161 162 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 163 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 164 } 165 166 def getIntWbArbiterParams: WbArbiterParams = { 167 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 168 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 169 } 170 171 def getVfWbArbiterParams: WbArbiterParams = { 172 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 173 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 174 } 175 176 def getFpWbArbiterParams: WbArbiterParams = { 177 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 178 datapath.WbArbiterParams(fpWbCfgs, vfPregParams, this) 179 } 180 181 /** 182 * Get regfile read port params 183 * 184 * @param dataCfg [[IntData]] or [[VecData]] 185 * @return Seq[port->Seq[(exuIdx, priority)] 186 */ 187 def getRdPortParams(dataCfg: DataConfig) = { 188 // port -> Seq[exuIdx, priority] 189 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 190 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 191 .filter { x => x._1.getDataConfig == dataCfg } 192 .map(x => (x._1.port, (x._2, x._1.priority))) 193 .groupBy(_._1) 194 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 195 .toSeq 196 .sortBy(_._1) 197 cfgs 198 } 199 200 /** 201 * Get regfile write back port params 202 * 203 * @param dataCfg [[IntData]] or [[VecData]] 204 * @return Seq[port->Seq[(exuIdx, priority)] 205 */ 206 def getWbPortParams(dataCfg: DataConfig) = { 207 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 208 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 209 .filter { x => x._1.dataCfg == dataCfg } 210 .map(x => (x._1.port, (x._2, x._1.priority))) 211 .groupBy(_._1) 212 .map(x => (x._1, x._2.map(_._2))) 213 .toSeq 214 .sortBy(_._1) 215 cfgs 216 } 217 218 def getRdPortIndices(dataCfg: DataConfig) = { 219 this.getRdPortParams(dataCfg).map(_._1) 220 } 221 222 def getWbPortIndices(dataCfg: DataConfig) = { 223 this.getWbPortParams(dataCfg).map(_._1) 224 } 225 226 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 227 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 228 _.exuBlockParams.map( 229 _.rfrPortConfigs.map( 230 _.collectFirst{ case x: T => x } 231 .getOrElse(NoRD()) 232 ) 233 ) 234 ) 235 rdCfgs 236 } 237 238 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 239 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 240 } 241 242 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 243 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 244 wbCfgs 245 } 246 247 /** 248 * Get size of read ports of int regfile 249 * 250 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 251 */ 252 def getIntRfReadSize = { 253 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 254 } 255 256 /** 257 * Get size of write ports of int regfile 258 * 259 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 260 */ 261 def getIntRfWriteSize = { 262 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 263 } 264 265 /** 266 * Get size of write ports of fp regfile 267 * 268 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 269 */ 270 def getFpRfWriteSize = { 271 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 272 } 273 274 /** 275 * Get size of read ports of vec regfile 276 * 277 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 278 */ 279 def getVfRfReadSize = { 280 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 281 } 282 283 /** 284 * Get size of write ports of vec regfile 285 * 286 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 287 */ 288 def getVfRfWriteSize = { 289 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 290 } 291 292 def getV0RfWriteSize = { 293 this.v0PregParams.numWrite.getOrElse(this.getWbPortIndices(V0Data()).size) 294 } 295 296 def getVlRfWriteSize = { 297 this.vlPregParams.numWrite.getOrElse(this.getWbPortIndices(VlData()).size) 298 } 299 300 def getRfReadSize(dataCfg: DataConfig) = { 301 dataCfg match{ 302 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 303 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 304 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 305 case V0Data() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 306 case VlData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 307 case _ => throw new IllegalArgumentException(s"DataConfig ${dataCfg} can not get RfReadSize") 308 } 309 } 310 311 def getRfWriteSize(dataCfg: DataConfig) = { 312 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 313 } 314 315 def getExuIdx(name: String): Int = { 316 val exuParams = allRealExuParams 317 if (name != "WB") { 318 val foundExu = exuParams.find(_.name == name) 319 require(foundExu.nonEmpty, s"exu $name not find") 320 foundExu.get.exuIdx 321 } else 322 -1 323 } 324 325 def getExuName(idx: Int): String = { 326 val exuParams = allRealExuParams 327 exuParams(idx).name 328 } 329 330 def getExuParamByName(name: String): ExeUnitParams = { 331 val exuParams = allExuParams 332 exuParams.find(_.name == name).get 333 } 334 335 def getLdExuIdx(exu: ExeUnitParams): Int = { 336 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 337 ldExuParams.indexOf(exu) 338 } 339 340 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 341 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 342 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 343 def getV0WBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 344 def getVlWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 345 346 private def isContinuous(portIndices: Seq[Int]): Boolean = { 347 val portIndicesSet = portIndices.toSet 348 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 349 } 350 351 def configChecks = { 352 checkReadPortContinuous 353 checkWritePortContinuous 354 configCheck 355 } 356 357 def checkReadPortContinuous = { 358 pregParams.filterNot(_.isFake).foreach { x => 359 if (x.numRead.isEmpty) { 360 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 361 require(isContinuous(portIndices), 362 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 363 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 364 } 365 } 366 } 367 368 def checkWritePortContinuous = { 369 pregParams.filterNot(_.isFake).foreach { x => 370 if (x.numWrite.isEmpty) { 371 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 372 require( 373 isContinuous(portIndices), 374 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 375 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 376 ) 377 } 378 } 379 } 380 381 def configCheck = { 382 // check 0 383 val maxPortSource = 4 384 385 allRealExuParams.map { 386 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 387 }.filter(_.isDefined).groupBy(_.get.port).foreach { 388 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 389 } 390 allRealExuParams.map { 391 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 392 }.filter(_.isDefined).groupBy(_.get.port).foreach { 393 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 394 } 395 396 // check 1 397 // if some exus share the same wb port and rd ports, 398 // the exu with high priority at wb must also have high priority at rd. 399 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 400 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 401 for(wbType <- wbTypes){ 402 for(rdType <- rdTypes){ 403 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 404 allRealExuParams.map { 405 case exuParam => 406 val wbPortConfigs = exuParam.wbPortConfigs 407 val wbConfigs = wbType match{ 408 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 409 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 410 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 411 case _ => None 412 } 413 val rfReadPortConfigs = exuParam.rfrPortConfigs 414 val rdConfigs = rdType match{ 415 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 416 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 417 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 418 case _ => Seq() 419 } 420 (wbConfigs, rdConfigs) 421 }.filter(_._1.isDefined) 422 .sortBy(_._1.get.priority) 423 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 424 val rdCfgs = intWbRdPairs.map(_._2).flatten 425 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 426 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 427 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 428 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 429 } 430 } 431 } 432 } 433 } 434} 435