1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 configChecks 42 43 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 44 45 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 46 47 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 48 copyPdestInfo.addOne(x) 49 } 50 def isCopyPdest(exuIdx: Int): Boolean = { 51 copyPdestInfo.contains(exuIdx) 52 } 53 def connectWakeup(exuIdx: Int): Unit = { 54 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 55 if (copyPdestInfo.contains(exuIdx)) { 56 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 57 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 58 copyPdestInfo.remove(exuIdx) 59 copyPdestInfo += newInfo 60 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 61 } 62 } 63 def getCopyPdestIndex(exuIdx: Int): Int = { 64 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 65 } 66 def intSchdParams = schdParams.get(IntScheduler()) 67 def vfSchdParams = schdParams.get(VfScheduler()) 68 def memSchdParams = schdParams.get(MemScheduler()) 69 def allSchdParams: Seq[SchdBlockParams] = 70 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 71 .filter(_.nonEmpty) 72 .map(_.get) 73 def allIssueParams: Seq[IssueBlockParams] = 74 allSchdParams.map(_.issueBlockParams).flatten 75 def allExuParams: Seq[ExeUnitParams] = 76 allIssueParams.map(_.exuBlockParams).flatten 77 78 // filter not fake exu unit 79 def allRealExuParams = 80 allExuParams.filterNot(_.fakeUnit) 81 82 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def getPregParams: Map[DataConfig, PregParams] = { 85 pregParams.map(x => (x.dataCfg, x)).toMap 86 } 87 88 def pregIdxWidth = pregParams.map(_.addrWidth).max 89 90 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 91 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 92 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 93 94 95 def AluCnt = allSchdParams.map(_.AluCnt).sum 96 def StaCnt = allSchdParams.map(_.StaCnt).sum 97 def StdCnt = allSchdParams.map(_.StdCnt).sum 98 def LduCnt = allSchdParams.map(_.LduCnt).sum 99 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 100 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 101 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 102 def LsExuCnt = StaCnt + LduCnt + HyuCnt 103 val LdExuCnt = LduCnt + HyuCnt 104 val StaExuCnt = StaCnt + HyuCnt 105 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 106 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 107 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 108 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 109 110 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 111 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 112 113 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 114 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 115 116 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 117 def numExu = allSchdParams.map(_.numExu).sum 118 def vconfigPort = 13 // Todo: remove it 119 def vldPort = 14 120 121 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 122 123 def numRedirect = allSchdParams.map(_.numRedirect).sum 124 125 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 126 127 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 128 129 def genIntWriteBackBundle(implicit p: Parameters) = { 130 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 131 } 132 133 def genVfWriteBackBundle(implicit p: Parameters) = { 134 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 135 } 136 137 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 138 genIntWriteBackBundle ++ genVfWriteBackBundle 139 } 140 141 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 142 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 143 } 144 145 def getIntWbArbiterParams: WbArbiterParams = { 146 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 147 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 148 } 149 150 def getVfWbArbiterParams: WbArbiterParams = { 151 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 152 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 153 } 154 155 /** 156 * Get regfile read port params 157 * 158 * @param dataCfg [[IntData]] or [[VecData]] 159 * @return Seq[port->Seq[(exuIdx, priority)] 160 */ 161 def getRdPortParams(dataCfg: DataConfig) = { 162 // port -> Seq[exuIdx, priority] 163 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 164 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 165 .filter { x => x._1.getDataConfig == dataCfg } 166 .map(x => (x._1.port, (x._2, x._1.priority))) 167 .groupBy(_._1) 168 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 169 .toSeq 170 .sortBy(_._1) 171 cfgs 172 } 173 174 /** 175 * Get regfile write back port params 176 * 177 * @param dataCfg [[IntData]] or [[VecData]] 178 * @return Seq[port->Seq[(exuIdx, priority)] 179 */ 180 def getWbPortParams(dataCfg: DataConfig) = { 181 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 182 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 183 .filter { x => x._1.dataCfg == dataCfg } 184 .map(x => (x._1.port, (x._2, x._1.priority))) 185 .groupBy(_._1) 186 .map(x => (x._1, x._2.map(_._2))) 187 .toSeq 188 .sortBy(_._1) 189 cfgs 190 } 191 192 def getRdPortIndices(dataCfg: DataConfig) = { 193 this.getRdPortParams(dataCfg).map(_._1) 194 } 195 196 def getWbPortIndices(dataCfg: DataConfig) = { 197 this.getWbPortParams(dataCfg).map(_._1) 198 } 199 200 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 201 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 202 _.exuBlockParams.map( 203 _.rfrPortConfigs.map( 204 _.collectFirst{ case x: T => x } 205 .getOrElse(NoRD()) 206 ) 207 ) 208 ) 209 rdCfgs 210 } 211 212 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 213 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 214 } 215 216 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 217 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 218 wbCfgs 219 } 220 221 /** 222 * Get size of read ports of int regfile 223 * 224 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 225 */ 226 def getIntRfReadSize = { 227 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 228 } 229 230 /** 231 * Get size of write ports of vf regfile 232 * 233 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 234 */ 235 def getIntRfWriteSize = { 236 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 237 } 238 239 /** 240 * Get size of read ports of int regfile 241 * 242 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 243 */ 244 def getVfRfReadSize = { 245 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 246 } 247 248 /** 249 * Get size of write ports of vf regfile 250 * 251 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 252 */ 253 def getVfRfWriteSize = { 254 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 255 } 256 257 def getRfReadSize(dataCfg: DataConfig) = { 258 dataCfg match{ 259 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 260 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) + 2 261 } 262 } 263 264 def getRfWriteSize(dataCfg: DataConfig) = { 265 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 266 } 267 268 def getExuIdx(name: String): Int = { 269 val exuParams = allRealExuParams 270 if (name != "WB") { 271 val foundExu = exuParams.find(_.name == name) 272 require(foundExu.nonEmpty, s"exu $name not find") 273 foundExu.get.exuIdx 274 } else 275 -1 276 } 277 278 def getExuName(idx: Int): String = { 279 val exuParams = allRealExuParams 280 exuParams(idx).name 281 } 282 283 def getExuParamByName(name: String): ExeUnitParams = { 284 val exuParams = allExuParams 285 exuParams.find(_.name == name).get 286 } 287 288 def getLdExuIdx(exu: ExeUnitParams): Int = { 289 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 290 ldExuParams.indexOf(exu) 291 } 292 293 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 294 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 295 296 private def isContinuous(portIndices: Seq[Int]): Boolean = { 297 val portIndicesSet = portIndices.toSet 298 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 299 } 300 301 def configChecks = { 302 checkReadPortContinuous 303 checkWritePortContinuous 304 configCheck 305 } 306 307 def checkReadPortContinuous = { 308 pregParams.foreach { x => 309 if (x.numRead.isEmpty) { 310 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 311 require(isContinuous(portIndices), 312 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 313 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 314 } 315 } 316 } 317 318 def checkWritePortContinuous = { 319 pregParams.foreach { x => 320 if (x.numWrite.isEmpty) { 321 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 322 require( 323 isContinuous(portIndices), 324 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 325 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 326 ) 327 } 328 } 329 } 330 331 def configCheck = { 332 // check 0 333 val maxPortSource = 4 334 335 allRealExuParams.map { 336 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 337 }.filter(_.isDefined).groupBy(_.get.port).foreach { 338 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 339 } 340 allRealExuParams.map { 341 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 342 }.filter(_.isDefined).groupBy(_.get.port).foreach { 343 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 344 } 345 346 // check 1 347 val wbTypes = Seq(IntWB(), VfWB()) 348 val rdTypes = Seq(IntRD(), VfRD()) 349 for(wbType <- wbTypes){ 350 for(rdType <- rdTypes){ 351 allRealExuParams.map { 352 case exuParam => 353 val wbPortConfigs = exuParam.wbPortConfigs 354 val wbConfigs = wbType match{ 355 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 356 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 357 case _ => None 358 } 359 val rfReadPortConfigs = exuParam.rfrPortConfigs 360 val rdConfigs = rdType match{ 361 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 362 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 363 case _ => Seq() 364 } 365 (wbConfigs, rdConfigs) 366 }.filter(_._1.isDefined) 367 .sortBy(_._1.get.priority) 368 .groupBy(_._1.get.port).map { 369 case (_, intWbRdPairs) => 370 intWbRdPairs.map(_._2).flatten 371 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 372 case (_, rdCfgs) => 373 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 374 }) 375 } 376 } 377 } 378} 379