1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 configChecks 42 43 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 44 45 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 46 47 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 48 copyPdestInfo.addOne(x) 49 } 50 def isCopyPdest(exuIdx: Int): Boolean = { 51 copyPdestInfo.contains(exuIdx) 52 } 53 def connectWakeup(exuIdx: Int): Unit = { 54 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 55 if (copyPdestInfo.contains(exuIdx)) { 56 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 57 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 58 copyPdestInfo.remove(exuIdx) 59 copyPdestInfo += newInfo 60 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 61 } 62 } 63 def getCopyPdestIndex(exuIdx: Int): Int = { 64 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 65 } 66 def intSchdParams = schdParams.get(IntScheduler()) 67 def vfSchdParams = schdParams.get(VfScheduler()) 68 def memSchdParams = schdParams.get(MemScheduler()) 69 def allSchdParams: Seq[SchdBlockParams] = 70 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 71 .filter(_.nonEmpty) 72 .map(_.get) 73 def allIssueParams: Seq[IssueBlockParams] = 74 allSchdParams.map(_.issueBlockParams).flatten 75 def allExuParams: Seq[ExeUnitParams] = 76 allIssueParams.map(_.exuBlockParams).flatten 77 78 // filter not fake exu unit 79 def allRealExuParams = 80 allExuParams.filterNot(_.fakeUnit) 81 82 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def getPregParams: Map[DataConfig, PregParams] = { 85 pregParams.map(x => (x.dataCfg, x)).toMap 86 } 87 88 def pregIdxWidth = pregParams.map(_.addrWidth).max 89 90 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 91 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 92 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 93 94 95 def AluCnt = allSchdParams.map(_.AluCnt).sum 96 def StaCnt = allSchdParams.map(_.StaCnt).sum 97 def StdCnt = allSchdParams.map(_.StdCnt).sum 98 def LduCnt = allSchdParams.map(_.LduCnt).sum 99 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 100 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 101 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 102 def LsExuCnt = StaCnt + LduCnt + HyuCnt 103 val LdExuCnt = LduCnt + HyuCnt 104 val StaExuCnt = StaCnt + HyuCnt 105 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 106 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 107 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 108 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 109 110 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 111 def numPcMemReadPort = allExuParams.filter(_.needPc).size 112 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 113 114 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 115 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 116 117 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 118 def numExu = allSchdParams.map(_.numExu).sum 119 def vconfigPort = 13 // Todo: remove it 120 def vldPort = 14 121 122 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 123 124 def numRedirect = allSchdParams.map(_.numRedirect).sum 125 126 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 127 128 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 129 130 def genIntWriteBackBundle(implicit p: Parameters) = { 131 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 132 } 133 134 def genVfWriteBackBundle(implicit p: Parameters) = { 135 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 136 } 137 138 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 139 genIntWriteBackBundle ++ genVfWriteBackBundle 140 } 141 142 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 143 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 144 } 145 146 def getIntWbArbiterParams: WbArbiterParams = { 147 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 148 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 149 } 150 151 def getVfWbArbiterParams: WbArbiterParams = { 152 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 153 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 154 } 155 156 /** 157 * Get regfile read port params 158 * 159 * @param dataCfg [[IntData]] or [[VecData]] 160 * @return Seq[port->Seq[(exuIdx, priority)] 161 */ 162 def getRdPortParams(dataCfg: DataConfig) = { 163 // port -> Seq[exuIdx, priority] 164 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 165 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 166 .filter { x => x._1.getDataConfig == dataCfg } 167 .map(x => (x._1.port, (x._2, x._1.priority))) 168 .groupBy(_._1) 169 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 170 .toSeq 171 .sortBy(_._1) 172 cfgs 173 } 174 175 /** 176 * Get regfile write back port params 177 * 178 * @param dataCfg [[IntData]] or [[VecData]] 179 * @return Seq[port->Seq[(exuIdx, priority)] 180 */ 181 def getWbPortParams(dataCfg: DataConfig) = { 182 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 183 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 184 .filter { x => x._1.dataCfg == dataCfg } 185 .map(x => (x._1.port, (x._2, x._1.priority))) 186 .groupBy(_._1) 187 .map(x => (x._1, x._2.map(_._2))) 188 .toSeq 189 .sortBy(_._1) 190 cfgs 191 } 192 193 def getRdPortIndices(dataCfg: DataConfig) = { 194 this.getRdPortParams(dataCfg).map(_._1) 195 } 196 197 def getWbPortIndices(dataCfg: DataConfig) = { 198 this.getWbPortParams(dataCfg).map(_._1) 199 } 200 201 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 202 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 203 _.exuBlockParams.map( 204 _.rfrPortConfigs.map( 205 _.collectFirst{ case x: T => x } 206 .getOrElse(NoRD()) 207 ) 208 ) 209 ) 210 rdCfgs 211 } 212 213 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 214 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 215 } 216 217 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 218 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 219 wbCfgs 220 } 221 222 /** 223 * Get size of read ports of int regfile 224 * 225 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 226 */ 227 def getIntRfReadSize = { 228 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 229 } 230 231 /** 232 * Get size of write ports of vf regfile 233 * 234 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 235 */ 236 def getIntRfWriteSize = { 237 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 238 } 239 240 /** 241 * Get size of read ports of int regfile 242 * 243 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 244 */ 245 def getVfRfReadSize = { 246 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 247 } 248 249 /** 250 * Get size of write ports of vf regfile 251 * 252 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 253 */ 254 def getVfRfWriteSize = { 255 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 256 } 257 258 def getRfReadSize(dataCfg: DataConfig) = { 259 dataCfg match{ 260 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 261 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) + 2 262 } 263 } 264 265 def getRfWriteSize(dataCfg: DataConfig) = { 266 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 267 } 268 269 def getExuIdx(name: String): Int = { 270 val exuParams = allRealExuParams 271 if (name != "WB") { 272 val foundExu = exuParams.find(_.name == name) 273 require(foundExu.nonEmpty, s"exu $name not find") 274 foundExu.get.exuIdx 275 } else 276 -1 277 } 278 279 def getExuName(idx: Int): String = { 280 val exuParams = allRealExuParams 281 exuParams(idx).name 282 } 283 284 def getExuParamByName(name: String): ExeUnitParams = { 285 val exuParams = allExuParams 286 exuParams.find(_.name == name).get 287 } 288 289 def getLdExuIdx(exu: ExeUnitParams): Int = { 290 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 291 ldExuParams.indexOf(exu) 292 } 293 294 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 295 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 296 297 private def isContinuous(portIndices: Seq[Int]): Boolean = { 298 val portIndicesSet = portIndices.toSet 299 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 300 } 301 302 def configChecks = { 303 checkReadPortContinuous 304 checkWritePortContinuous 305 configCheck 306 } 307 308 def checkReadPortContinuous = { 309 pregParams.foreach { x => 310 if (x.numRead.isEmpty) { 311 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 312 require(isContinuous(portIndices), 313 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 314 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 315 } 316 } 317 } 318 319 def checkWritePortContinuous = { 320 pregParams.foreach { x => 321 if (x.numWrite.isEmpty) { 322 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 323 require( 324 isContinuous(portIndices), 325 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 326 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 327 ) 328 } 329 } 330 } 331 332 def configCheck = { 333 // check 0 334 val maxPortSource = 4 335 336 allRealExuParams.map { 337 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 338 }.filter(_.isDefined).groupBy(_.get.port).foreach { 339 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 340 } 341 allRealExuParams.map { 342 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 343 }.filter(_.isDefined).groupBy(_.get.port).foreach { 344 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 345 } 346 347 // check 1 348 val wbTypes = Seq(IntWB(), VfWB()) 349 val rdTypes = Seq(IntRD(), VfRD()) 350 for(wbType <- wbTypes){ 351 for(rdType <- rdTypes){ 352 allRealExuParams.map { 353 case exuParam => 354 val wbPortConfigs = exuParam.wbPortConfigs 355 val wbConfigs = wbType match{ 356 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 357 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 358 case _ => None 359 } 360 val rfReadPortConfigs = exuParam.rfrPortConfigs 361 val rdConfigs = rdType match{ 362 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 363 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 364 case _ => Seq() 365 } 366 (wbConfigs, rdConfigs) 367 }.filter(_._1.isDefined) 368 .sortBy(_._1.get.priority) 369 .groupBy(_._1.get.port).map { 370 case (_, intWbRdPairs) => 371 intWbRdPairs.map(_._2).flatten 372 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 373 case (_, rdCfgs) => 374 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 375 }) 376 } 377 } 378 } 379} 380