1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.reflect.{ClassTag, classTag} 33 34case class BackendParams( 35 schdParams : Map[SchedulerType, SchdBlockParams], 36 pregParams : Seq[PregParams], 37 iqWakeUpParams : Seq[WakeUpConfig], 38) { 39 40 configChecks 41 42 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 43 def intSchdParams = schdParams.get(IntScheduler()) 44 def vfSchdParams = schdParams.get(VfScheduler()) 45 def memSchdParams = schdParams.get(MemScheduler()) 46 def allSchdParams: Seq[SchdBlockParams] = 47 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 48 .filter(_.nonEmpty) 49 .map(_.get) 50 def allIssueParams: Seq[IssueBlockParams] = 51 allSchdParams.map(_.issueBlockParams).flatten 52 def allExuParams: Seq[ExeUnitParams] = 53 allIssueParams.map(_.exuBlockParams).flatten 54 55 // filter not fake exu unit 56 def allRealExuParams = 57 allExuParams.filterNot(_.fakeUnit) 58 59 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 60 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 61 def getPregParams: Map[DataConfig, PregParams] = { 62 pregParams.map(x => (x.dataCfg, x)).toMap 63 } 64 65 def pregIdxWidth = pregParams.map(_.addrWidth).max 66 67 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 68 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 69 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 70 71 72 def AluCnt = allSchdParams.map(_.AluCnt).sum 73 def StaCnt = allSchdParams.map(_.StaCnt).sum 74 def StdCnt = allSchdParams.map(_.StdCnt).sum 75 def LduCnt = allSchdParams.map(_.LduCnt).sum 76 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 77 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 78 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 79 def LsExuCnt = StaCnt + LduCnt + HyuCnt 80 val LdExuCnt = LduCnt + HyuCnt 81 val StaExuCnt = StaCnt + HyuCnt 82 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 83 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 84 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 85 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 86 87 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 88 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 89 90 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 91 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 92 93 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 94 def numExu = allSchdParams.map(_.numExu).sum 95 def vconfigPort = 13 // Todo: remove it 96 def vldPort = 14 97 98 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 99 100 def numRedirect = allSchdParams.map(_.numRedirect).sum 101 102 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 103 104 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 105 106 def genIntWriteBackBundle(implicit p: Parameters) = { 107 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 108 } 109 110 def genVfWriteBackBundle(implicit p: Parameters) = { 111 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 112 } 113 114 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 115 genIntWriteBackBundle ++ genVfWriteBackBundle 116 } 117 118 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 119 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 120 } 121 122 def getIntWbArbiterParams: WbArbiterParams = { 123 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 124 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 125 } 126 127 def getVfWbArbiterParams: WbArbiterParams = { 128 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 129 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 130 } 131 132 /** 133 * Get regfile read port params 134 * 135 * @param dataCfg [[IntData]] or [[VecData]] 136 * @return Seq[port->Seq[(exuIdx, priority)] 137 */ 138 def getRdPortParams(dataCfg: DataConfig) = { 139 // port -> Seq[exuIdx, priority] 140 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 141 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 142 .filter { x => x._1.getDataConfig == dataCfg } 143 .map(x => (x._1.port, (x._2, x._1.priority))) 144 .groupBy(_._1) 145 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 146 .toSeq 147 .sortBy(_._1) 148 cfgs 149 } 150 151 /** 152 * Get regfile write back port params 153 * 154 * @param dataCfg [[IntData]] or [[VecData]] 155 * @return Seq[port->Seq[(exuIdx, priority)] 156 */ 157 def getWbPortParams(dataCfg: DataConfig) = { 158 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 159 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 160 .filter { x => x._1.dataCfg == dataCfg } 161 .map(x => (x._1.port, (x._2, x._1.priority))) 162 .groupBy(_._1) 163 .map(x => (x._1, x._2.map(_._2))) 164 .toSeq 165 .sortBy(_._1) 166 cfgs 167 } 168 169 def getRdPortIndices(dataCfg: DataConfig) = { 170 this.getRdPortParams(dataCfg).map(_._1) 171 } 172 173 def getWbPortIndices(dataCfg: DataConfig) = { 174 this.getWbPortParams(dataCfg).map(_._1) 175 } 176 177 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 178 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 179 _.exuBlockParams.map( 180 _.rfrPortConfigs.map( 181 _.collectFirst{ case x: T => x } 182 .getOrElse(NoRD()) 183 ) 184 ) 185 ) 186 rdCfgs 187 } 188 189 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 190 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 191 } 192 193 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 194 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 195 wbCfgs 196 } 197 198 /** 199 * Get size of read ports of int regfile 200 * 201 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 202 */ 203 def getIntRfReadSize = { 204 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 205 } 206 207 /** 208 * Get size of write ports of vf regfile 209 * 210 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 211 */ 212 def getIntRfWriteSize = { 213 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 214 } 215 216 /** 217 * Get size of read ports of int regfile 218 * 219 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 220 */ 221 def getVfRfReadSize = { 222 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 223 } 224 225 /** 226 * Get size of write ports of vf regfile 227 * 228 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 229 */ 230 def getVfRfWriteSize = { 231 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 232 } 233 234 def getRfReadSize(dataCfg: DataConfig) = { 235 dataCfg match{ 236 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 237 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) + 2 238 } 239 } 240 241 def getRfWriteSize(dataCfg: DataConfig) = { 242 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 243 } 244 245 def getExuIdx(name: String): Int = { 246 val exuParams = allRealExuParams 247 if (name != "WB") { 248 val foundExu = exuParams.find(_.name == name) 249 require(foundExu.nonEmpty, s"exu $name not find") 250 foundExu.get.exuIdx 251 } else 252 -1 253 } 254 255 def getExuName(idx: Int): String = { 256 val exuParams = allRealExuParams 257 exuParams(idx).name 258 } 259 260 def getExuParamByName(name: String): ExeUnitParams = { 261 val exuParams = allExuParams 262 exuParams.find(_.name == name).get 263 } 264 265 def getLdExuIdx(exu: ExeUnitParams): Int = { 266 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 267 ldExuParams.indexOf(exu) 268 } 269 270 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 271 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 272 273 private def isContinuous(portIndices: Seq[Int]): Boolean = { 274 val portIndicesSet = portIndices.toSet 275 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 276 } 277 278 def configChecks = { 279 checkReadPortContinuous 280 checkWritePortContinuous 281 configCheck 282 } 283 284 def checkReadPortContinuous = { 285 pregParams.foreach { x => 286 if (x.numRead.isEmpty) { 287 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 288 require(isContinuous(portIndices), 289 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 290 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 291 } 292 } 293 } 294 295 def checkWritePortContinuous = { 296 pregParams.foreach { x => 297 if (x.numWrite.isEmpty) { 298 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 299 require( 300 isContinuous(portIndices), 301 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 302 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 303 ) 304 } 305 } 306 } 307 308 def configCheck = { 309 // check 0 310 val maxPortSource = 4 311 312 allRealExuParams.map { 313 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 314 }.filter(_.isDefined).groupBy(_.get.port).foreach { 315 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 316 } 317 allRealExuParams.map { 318 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 319 }.filter(_.isDefined).groupBy(_.get.port).foreach { 320 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 321 } 322 323 // check 1 324 val wbTypes = Seq(IntWB(), VfWB()) 325 val rdTypes = Seq(IntRD(), VfRD()) 326 for(wbType <- wbTypes){ 327 for(rdType <- rdTypes){ 328 allRealExuParams.map { 329 case exuParam => 330 val wbPortConfigs = exuParam.wbPortConfigs 331 val wbConfigs = wbType match{ 332 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 333 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 334 case _ => None 335 } 336 val rfReadPortConfigs = exuParam.rfrPortConfigs 337 val rdConfigs = rdType match{ 338 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 339 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 340 case _ => Seq() 341 } 342 (wbConfigs, rdConfigs) 343 }.filter(_._1.isDefined) 344 .sortBy(_._1.get.priority) 345 .groupBy(_._1.get.port).map { 346 case (_, intWbRdPairs) => 347 intWbRdPairs.map(_._2).flatten 348 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 349 case (_, rdCfgs) => 350 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 351 }) 352 } 353 } 354 } 355} 356