1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.DebugOptionsKey 31 32import scala.reflect.{ClassTag, classTag} 33 34case class BackendParams( 35 schdParams : Map[SchedulerType, SchdBlockParams], 36 pregParams : Seq[PregParams], 37 iqWakeUpParams : Seq[WakeUpConfig], 38) { 39 40 configChecks 41 42 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 43 def intSchdParams = schdParams.get(IntScheduler()) 44 def vfSchdParams = schdParams.get(VfScheduler()) 45 def memSchdParams = schdParams.get(MemScheduler()) 46 def allSchdParams: Seq[SchdBlockParams] = 47 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 48 .filter(_.nonEmpty) 49 .map(_.get) 50 def allIssueParams: Seq[IssueBlockParams] = 51 allSchdParams.map(_.issueBlockParams).flatten 52 def allExuParams: Seq[ExeUnitParams] = 53 allIssueParams.map(_.exuBlockParams).flatten 54 55 // filter not fake exu unit 56 def allRealExuParams = 57 allExuParams.filterNot(_.fakeUnit) 58 59 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 60 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 61 def getPregParams: Map[DataConfig, PregParams] = { 62 pregParams.map(x => (x.dataCfg, x)).toMap 63 } 64 65 def pregIdxWidth = pregParams.map(_.addrWidth).max 66 67 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 68 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 69 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 70 71 72 def AluCnt = allSchdParams.map(_.AluCnt).sum 73 def StaCnt = allSchdParams.map(_.StaCnt).sum 74 def StdCnt = allSchdParams.map(_.StdCnt).sum 75 def LduCnt = allSchdParams.map(_.LduCnt).sum 76 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 77 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 78 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 79 def LsExuCnt = StaCnt + LduCnt + HyuCnt 80 val LdExuCnt = LduCnt + HyuCnt 81 val StaExuCnt = StaCnt + HyuCnt 82 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 83 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 84 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 85 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 86 87 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 88 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 89 90 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 91 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 92 93 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 94 def numExu = allSchdParams.map(_.numExu).sum 95 def vconfigPort = 13 // Todo: remove it 96 def vldPort = 14 97 98 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 99 100 def numRedirect = allSchdParams.map(_.numRedirect).sum 101 102 def genIntWriteBackBundle(implicit p: Parameters) = { 103 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 104 } 105 106 def genVfWriteBackBundle(implicit p: Parameters) = { 107 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 108 } 109 110 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 111 genIntWriteBackBundle ++ genVfWriteBackBundle 112 } 113 114 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 115 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 116 } 117 118 def getIntWbArbiterParams: WbArbiterParams = { 119 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 120 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 121 } 122 123 def getVfWbArbiterParams: WbArbiterParams = { 124 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 125 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 126 } 127 128 /** 129 * Get regfile read port params 130 * 131 * @param dataCfg [[IntData]] or [[VecData]] 132 * @return Seq[port->Seq[(exuIdx, priority)] 133 */ 134 def getRdPortParams(dataCfg: DataConfig) = { 135 // port -> Seq[exuIdx, priority] 136 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 137 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 138 .filter { x => x._1.getDataConfig == dataCfg } 139 .map(x => (x._1.port, (x._2, x._1.priority))) 140 .groupBy(_._1) 141 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 142 .toSeq 143 .sortBy(_._1) 144 cfgs 145 } 146 147 /** 148 * Get regfile write back port params 149 * 150 * @param dataCfg [[IntData]] or [[VecData]] 151 * @return Seq[port->Seq[(exuIdx, priority)] 152 */ 153 def getWbPortParams(dataCfg: DataConfig) = { 154 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 155 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 156 .filter { x => x._1.dataCfg == dataCfg } 157 .map(x => (x._1.port, (x._2, x._1.priority))) 158 .groupBy(_._1) 159 .map(x => (x._1, x._2.map(_._2))) 160 .toSeq 161 .sortBy(_._1) 162 cfgs 163 } 164 165 def getRdPortIndices(dataCfg: DataConfig) = { 166 this.getRdPortParams(dataCfg).map(_._1) 167 } 168 169 def getWbPortIndices(dataCfg: DataConfig) = { 170 this.getWbPortParams(dataCfg).map(_._1) 171 } 172 173 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 174 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 175 _.exuBlockParams.map( 176 _.rfrPortConfigs.map( 177 _.collectFirst{ case x: T => x } 178 .getOrElse(NoRD()) 179 ) 180 ) 181 ) 182 rdCfgs 183 } 184 185 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 186 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 187 } 188 189 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 190 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 191 wbCfgs 192 } 193 194 /** 195 * Get size of read ports of int regfile 196 * 197 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 198 */ 199 def getIntRfReadSize = { 200 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 201 } 202 203 /** 204 * Get size of write ports of vf regfile 205 * 206 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 207 */ 208 def getIntRfWriteSize = { 209 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 210 } 211 212 /** 213 * Get size of read ports of int regfile 214 * 215 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 216 */ 217 def getVfRfReadSize = { 218 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 219 } 220 221 /** 222 * Get size of write ports of vf regfile 223 * 224 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 225 */ 226 def getVfRfWriteSize = { 227 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 228 } 229 230 def getRfReadSize(dataCfg: DataConfig) = { 231 dataCfg match{ 232 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 233 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) + 2 234 } 235 } 236 237 def getRfWriteSize(dataCfg: DataConfig) = { 238 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 239 } 240 241 def getExuIdx(name: String): Int = { 242 val exuParams = allRealExuParams 243 if (name != "WB") { 244 val foundExu = exuParams.find(_.name == name) 245 require(foundExu.nonEmpty, s"exu $name not find") 246 foundExu.get.exuIdx 247 } else 248 -1 249 } 250 251 def getExuName(idx: Int): String = { 252 val exuParams = allRealExuParams 253 exuParams(idx).name 254 } 255 256 def getExuParamByName(name: String): ExeUnitParams = { 257 val exuParams = allExuParams 258 exuParams.find(_.name == name).get 259 } 260 261 def getLdExuIdx(exu: ExeUnitParams): Int = { 262 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 263 ldExuParams.indexOf(exu) 264 } 265 266 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 267 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 268 269 private def isContinuous(portIndices: Seq[Int]): Boolean = { 270 val portIndicesSet = portIndices.toSet 271 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 272 } 273 274 def configChecks = { 275 checkReadPortContinuous 276 checkWritePortContinuous 277 configCheck 278 } 279 280 def checkReadPortContinuous = { 281 pregParams.foreach { x => 282 if (x.numRead.isEmpty) { 283 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 284 require(isContinuous(portIndices), 285 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 286 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 287 } 288 } 289 } 290 291 def checkWritePortContinuous = { 292 pregParams.foreach { x => 293 if (x.numWrite.isEmpty) { 294 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 295 require( 296 isContinuous(portIndices), 297 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 298 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 299 ) 300 } 301 } 302 } 303 304 def configCheck = { 305 // check 0 306 val maxPortSource = 4 307 308 allRealExuParams.map { 309 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 310 }.filter(_.isDefined).groupBy(_.get.port).foreach { 311 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 312 } 313 allRealExuParams.map { 314 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 315 }.filter(_.isDefined).groupBy(_.get.port).foreach { 316 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 317 } 318 319 // check 1 320 val wbTypes = Seq(IntWB(), VfWB()) 321 val rdTypes = Seq(IntRD(), VfRD()) 322 for(wbType <- wbTypes){ 323 for(rdType <- rdTypes){ 324 allRealExuParams.map { 325 case exuParam => 326 val wbPortConfigs = exuParam.wbPortConfigs 327 val wbConfigs = wbType match{ 328 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 329 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 330 case _ => None 331 } 332 val rfReadPortConfigs = exuParam.rfrPortConfigs 333 val rdConfigs = rdType match{ 334 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 335 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 336 case _ => Seq() 337 } 338 (wbConfigs, rdConfigs) 339 }.filter(_._1.isDefined) 340 .sortBy(_._1.get.priority) 341 .groupBy(_._1.get.port).map { 342 case (_, intWbRdPairs) => 343 intWbRdPairs.map(_._2).flatten 344 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 345 case (_, rdCfgs) => 346 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 347 }) 348 } 349 } 350 } 351} 352