1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 42 43 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 44 45 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 46 copyPdestInfo.addOne(x) 47 } 48 def isCopyPdest(exuIdx: Int): Boolean = { 49 copyPdestInfo.contains(exuIdx) 50 } 51 def connectWakeup(exuIdx: Int): Unit = { 52 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 53 if (copyPdestInfo.contains(exuIdx)) { 54 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 55 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 56 copyPdestInfo.remove(exuIdx) 57 copyPdestInfo += newInfo 58 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 59 } 60 } 61 def getCopyPdestIndex(exuIdx: Int): Int = { 62 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 63 } 64 def intSchdParams = schdParams.get(IntScheduler()) 65 def fpSchdParams = schdParams.get(FpScheduler()) 66 def vfSchdParams = schdParams.get(VfScheduler()) 67 def memSchdParams = schdParams.get(MemScheduler()) 68 def allSchdParams: Seq[SchdBlockParams] = 69 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 70 .filter(_.nonEmpty) 71 .map(_.get) 72 def allIssueParams: Seq[IssueBlockParams] = 73 allSchdParams.map(_.issueBlockParams).flatten 74 def allExuParams: Seq[ExeUnitParams] = 75 allIssueParams.map(_.exuBlockParams).flatten 76 77 // filter not fake exu unit 78 def allRealExuParams = 79 allExuParams.filterNot(_.fakeUnit) 80 81 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 82 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def getPregParams: Map[DataConfig, PregParams] = { 85 pregParams.map(x => (x.dataCfg, x)).toMap 86 } 87 88 def pregIdxWidth = pregParams.map(_.addrWidth).max 89 90 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 91 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 92 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 93 94 95 def AluCnt = allSchdParams.map(_.AluCnt).sum 96 def StaCnt = allSchdParams.map(_.StaCnt).sum 97 def StdCnt = allSchdParams.map(_.StdCnt).sum 98 def LduCnt = allSchdParams.map(_.LduCnt).sum 99 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 100 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 101 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 102 def LsExuCnt = StaCnt + LduCnt + HyuCnt 103 val LdExuCnt = LduCnt + HyuCnt 104 val StaExuCnt = StaCnt + HyuCnt 105 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 106 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 107 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 108 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 109 110 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 111 def numPcMemReadPort = allExuParams.filter(_.needPc).size 112 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 113 114 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 115 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 116 117 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 118 def numExu = allSchdParams.map(_.numExu).sum 119 120 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 121 122 def numRedirect = allSchdParams.map(_.numRedirect).sum 123 124 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 125 126 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 127 128 def genIntIQValidNumBundle(implicit p: Parameters) = { 129 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 130 } 131 132 def genFpIQValidNumBundle(implicit p: Parameters) = { 133 this.fpSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 134 } 135 136 def genIntWriteBackBundle(implicit p: Parameters) = { 137 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 138 } 139 140 def genFpWriteBackBundle(implicit p: Parameters) = { 141 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 142 } 143 144 def genVfWriteBackBundle(implicit p: Parameters) = { 145 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 146 } 147 148 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 149 genIntWriteBackBundle ++ genVfWriteBackBundle 150 } 151 152 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 153 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 154 } 155 156 def getIntWbArbiterParams: WbArbiterParams = { 157 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 158 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 159 } 160 161 def getVfWbArbiterParams: WbArbiterParams = { 162 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 163 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 164 } 165 166 def getFpWbArbiterParams: WbArbiterParams = { 167 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 168 datapath.WbArbiterParams(fpWbCfgs, vfPregParams, this) 169 } 170 171 /** 172 * Get regfile read port params 173 * 174 * @param dataCfg [[IntData]] or [[VecData]] 175 * @return Seq[port->Seq[(exuIdx, priority)] 176 */ 177 def getRdPortParams(dataCfg: DataConfig) = { 178 // port -> Seq[exuIdx, priority] 179 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 180 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 181 .filter { x => x._1.getDataConfig == dataCfg } 182 .map(x => (x._1.port, (x._2, x._1.priority))) 183 .groupBy(_._1) 184 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 185 .toSeq 186 .sortBy(_._1) 187 cfgs 188 } 189 190 /** 191 * Get regfile write back port params 192 * 193 * @param dataCfg [[IntData]] or [[VecData]] 194 * @return Seq[port->Seq[(exuIdx, priority)] 195 */ 196 def getWbPortParams(dataCfg: DataConfig) = { 197 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 198 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 199 .filter { x => x._1.dataCfg == dataCfg } 200 .map(x => (x._1.port, (x._2, x._1.priority))) 201 .groupBy(_._1) 202 .map(x => (x._1, x._2.map(_._2))) 203 .toSeq 204 .sortBy(_._1) 205 cfgs 206 } 207 208 def getRdPortIndices(dataCfg: DataConfig) = { 209 this.getRdPortParams(dataCfg).map(_._1) 210 } 211 212 def getWbPortIndices(dataCfg: DataConfig) = { 213 this.getWbPortParams(dataCfg).map(_._1) 214 } 215 216 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 217 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 218 _.exuBlockParams.map( 219 _.rfrPortConfigs.map( 220 _.collectFirst{ case x: T => x } 221 .getOrElse(NoRD()) 222 ) 223 ) 224 ) 225 rdCfgs 226 } 227 228 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 229 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 230 } 231 232 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 233 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 234 wbCfgs 235 } 236 237 /** 238 * Get size of read ports of int regfile 239 * 240 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 241 */ 242 def getIntRfReadSize = { 243 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 244 } 245 246 /** 247 * Get size of write ports of vf regfile 248 * 249 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 250 */ 251 def getIntRfWriteSize = { 252 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 253 } 254 255 /** 256 * Get size of write ports of fp regfile 257 * 258 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 259 */ 260 def getFpRfWriteSize = { 261 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 262 } 263 264 /** 265 * Get size of read ports of int regfile 266 * 267 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 268 */ 269 def getVfRfReadSize = { 270 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 271 } 272 273 /** 274 * Get size of write ports of vf regfile 275 * 276 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 277 */ 278 def getVfRfWriteSize = { 279 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 280 } 281 282 def getRfReadSize(dataCfg: DataConfig) = { 283 dataCfg match{ 284 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 285 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 286 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 287 } 288 } 289 290 def getRfWriteSize(dataCfg: DataConfig) = { 291 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 292 } 293 294 def getExuIdx(name: String): Int = { 295 val exuParams = allRealExuParams 296 if (name != "WB") { 297 val foundExu = exuParams.find(_.name == name) 298 require(foundExu.nonEmpty, s"exu $name not find") 299 foundExu.get.exuIdx 300 } else 301 -1 302 } 303 304 def getExuName(idx: Int): String = { 305 val exuParams = allRealExuParams 306 exuParams(idx).name 307 } 308 309 def getExuParamByName(name: String): ExeUnitParams = { 310 val exuParams = allExuParams 311 exuParams.find(_.name == name).get 312 } 313 314 def getLdExuIdx(exu: ExeUnitParams): Int = { 315 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 316 ldExuParams.indexOf(exu) 317 } 318 319 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 320 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 321 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 322 323 private def isContinuous(portIndices: Seq[Int]): Boolean = { 324 val portIndicesSet = portIndices.toSet 325 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 326 } 327 328 def configChecks = { 329 checkReadPortContinuous 330 checkWritePortContinuous 331 configCheck 332 } 333 334 def checkReadPortContinuous = { 335 pregParams.filterNot(_.isFake).foreach { x => 336 if (x.numRead.isEmpty) { 337 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 338 require(isContinuous(portIndices), 339 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 340 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 341 } 342 } 343 } 344 345 def checkWritePortContinuous = { 346 pregParams.filterNot(_.isFake).foreach { x => 347 if (x.numWrite.isEmpty) { 348 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 349 require( 350 isContinuous(portIndices), 351 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 352 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 353 ) 354 } 355 } 356 } 357 358 def configCheck = { 359 // check 0 360 val maxPortSource = 4 361 362 allRealExuParams.map { 363 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 364 }.filter(_.isDefined).groupBy(_.get.port).foreach { 365 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 366 } 367 allRealExuParams.map { 368 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 369 }.filter(_.isDefined).groupBy(_.get.port).foreach { 370 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 371 } 372 373 // check 1 374 // if some exus share the same wb port and rd ports, 375 // the exu with high priority at wb must also have high priority at rd. 376 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 377 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 378 for(wbType <- wbTypes){ 379 for(rdType <- rdTypes){ 380 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 381 allRealExuParams.map { 382 case exuParam => 383 val wbPortConfigs = exuParam.wbPortConfigs 384 val wbConfigs = wbType match{ 385 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 386 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 387 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 388 case _ => None 389 } 390 val rfReadPortConfigs = exuParam.rfrPortConfigs 391 val rdConfigs = rdType match{ 392 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 393 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 394 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 395 case _ => Seq() 396 } 397 (wbConfigs, rdConfigs) 398 }.filter(_._1.isDefined) 399 .sortBy(_._1.get.priority) 400 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 401 val rdCfgs = intWbRdPairs.map(_._2).flatten 402 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 403 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 404 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 405 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 406 } 407 } 408 } 409 } 410 } 411} 412