1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 configChecks 42 43 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 44 45 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 46 47 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 48 copyPdestInfo.addOne(x) 49 } 50 def isCopyPdest(exuIdx: Int): Boolean = { 51 copyPdestInfo.contains(exuIdx) 52 } 53 def connectWakeup(exuIdx: Int): Unit = { 54 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 55 if (copyPdestInfo.contains(exuIdx)) { 56 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 57 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 58 copyPdestInfo.remove(exuIdx) 59 copyPdestInfo += newInfo 60 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 61 } 62 } 63 def getCopyPdestIndex(exuIdx: Int): Int = { 64 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 65 } 66 def intSchdParams = schdParams.get(IntScheduler()) 67 def vfSchdParams = schdParams.get(VfScheduler()) 68 def memSchdParams = schdParams.get(MemScheduler()) 69 def allSchdParams: Seq[SchdBlockParams] = 70 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 71 .filter(_.nonEmpty) 72 .map(_.get) 73 def allIssueParams: Seq[IssueBlockParams] = 74 allSchdParams.map(_.issueBlockParams).flatten 75 def allExuParams: Seq[ExeUnitParams] = 76 allIssueParams.map(_.exuBlockParams).flatten 77 78 // filter not fake exu unit 79 def allRealExuParams = 80 allExuParams.filterNot(_.fakeUnit) 81 82 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def getPregParams: Map[DataConfig, PregParams] = { 85 pregParams.map(x => (x.dataCfg, x)).toMap 86 } 87 88 def pregIdxWidth = pregParams.map(_.addrWidth).max 89 90 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 91 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 92 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 93 94 95 def AluCnt = allSchdParams.map(_.AluCnt).sum 96 def StaCnt = allSchdParams.map(_.StaCnt).sum 97 def StdCnt = allSchdParams.map(_.StdCnt).sum 98 def LduCnt = allSchdParams.map(_.LduCnt).sum 99 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 100 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 101 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 102 def LsExuCnt = StaCnt + LduCnt + HyuCnt 103 val LdExuCnt = LduCnt + HyuCnt 104 val StaExuCnt = StaCnt + HyuCnt 105 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 106 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 107 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 108 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 109 110 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 111 def numPcMemReadPort = allExuParams.filter(_.needPc).size 112 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 113 114 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 115 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 116 117 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 118 def numExu = allSchdParams.map(_.numExu).sum 119 120 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 121 122 def numRedirect = allSchdParams.map(_.numRedirect).sum 123 124 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 125 126 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 127 128 def genIQValidNumBundle(implicit p: Parameters) = { 129 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 130 } 131 132 def genIntWriteBackBundle(implicit p: Parameters) = { 133 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 134 } 135 136 def genVfWriteBackBundle(implicit p: Parameters) = { 137 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 138 } 139 140 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 141 genIntWriteBackBundle ++ genVfWriteBackBundle 142 } 143 144 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 145 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 146 } 147 148 def getIntWbArbiterParams: WbArbiterParams = { 149 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 150 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 151 } 152 153 def getVfWbArbiterParams: WbArbiterParams = { 154 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 155 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 156 } 157 158 /** 159 * Get regfile read port params 160 * 161 * @param dataCfg [[IntData]] or [[VecData]] 162 * @return Seq[port->Seq[(exuIdx, priority)] 163 */ 164 def getRdPortParams(dataCfg: DataConfig) = { 165 // port -> Seq[exuIdx, priority] 166 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 167 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 168 .filter { x => x._1.getDataConfig == dataCfg } 169 .map(x => (x._1.port, (x._2, x._1.priority))) 170 .groupBy(_._1) 171 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 172 .toSeq 173 .sortBy(_._1) 174 cfgs 175 } 176 177 /** 178 * Get regfile write back port params 179 * 180 * @param dataCfg [[IntData]] or [[VecData]] 181 * @return Seq[port->Seq[(exuIdx, priority)] 182 */ 183 def getWbPortParams(dataCfg: DataConfig) = { 184 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 185 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 186 .filter { x => x._1.dataCfg == dataCfg } 187 .map(x => (x._1.port, (x._2, x._1.priority))) 188 .groupBy(_._1) 189 .map(x => (x._1, x._2.map(_._2))) 190 .toSeq 191 .sortBy(_._1) 192 cfgs 193 } 194 195 def getRdPortIndices(dataCfg: DataConfig) = { 196 this.getRdPortParams(dataCfg).map(_._1) 197 } 198 199 def getWbPortIndices(dataCfg: DataConfig) = { 200 this.getWbPortParams(dataCfg).map(_._1) 201 } 202 203 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 204 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 205 _.exuBlockParams.map( 206 _.rfrPortConfigs.map( 207 _.collectFirst{ case x: T => x } 208 .getOrElse(NoRD()) 209 ) 210 ) 211 ) 212 rdCfgs 213 } 214 215 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 216 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 217 } 218 219 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 220 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 221 wbCfgs 222 } 223 224 /** 225 * Get size of read ports of int regfile 226 * 227 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 228 */ 229 def getIntRfReadSize = { 230 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 231 } 232 233 /** 234 * Get size of write ports of vf regfile 235 * 236 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 237 */ 238 def getIntRfWriteSize = { 239 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 240 } 241 242 /** 243 * Get size of read ports of int regfile 244 * 245 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 246 */ 247 def getVfRfReadSize = { 248 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 249 } 250 251 /** 252 * Get size of write ports of vf regfile 253 * 254 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 255 */ 256 def getVfRfWriteSize = { 257 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 258 } 259 260 def getRfReadSize(dataCfg: DataConfig) = { 261 dataCfg match{ 262 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 263 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) + 2 264 } 265 } 266 267 def getRfWriteSize(dataCfg: DataConfig) = { 268 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 269 } 270 271 def getExuIdx(name: String): Int = { 272 val exuParams = allRealExuParams 273 if (name != "WB") { 274 val foundExu = exuParams.find(_.name == name) 275 require(foundExu.nonEmpty, s"exu $name not find") 276 foundExu.get.exuIdx 277 } else 278 -1 279 } 280 281 def getExuName(idx: Int): String = { 282 val exuParams = allRealExuParams 283 exuParams(idx).name 284 } 285 286 def getExuParamByName(name: String): ExeUnitParams = { 287 val exuParams = allExuParams 288 exuParams.find(_.name == name).get 289 } 290 291 def getLdExuIdx(exu: ExeUnitParams): Int = { 292 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 293 ldExuParams.indexOf(exu) 294 } 295 296 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 297 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 298 299 private def isContinuous(portIndices: Seq[Int]): Boolean = { 300 val portIndicesSet = portIndices.toSet 301 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 302 } 303 304 def configChecks = { 305 checkReadPortContinuous 306 checkWritePortContinuous 307 configCheck 308 } 309 310 def checkReadPortContinuous = { 311 pregParams.filterNot(_.isFake).foreach { x => 312 if (x.numRead.isEmpty) { 313 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 314 require(isContinuous(portIndices), 315 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 316 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 317 } 318 } 319 } 320 321 def checkWritePortContinuous = { 322 pregParams.filterNot(_.isFake).foreach { x => 323 if (x.numWrite.isEmpty) { 324 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 325 require( 326 isContinuous(portIndices), 327 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 328 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 329 ) 330 } 331 } 332 } 333 334 def configCheck = { 335 // check 0 336 val maxPortSource = 4 337 338 allRealExuParams.map { 339 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 340 }.filter(_.isDefined).groupBy(_.get.port).foreach { 341 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 342 } 343 allRealExuParams.map { 344 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 345 }.filter(_.isDefined).groupBy(_.get.port).foreach { 346 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 347 } 348 349 // check 1 350 val wbTypes = Seq(IntWB(), VfWB()) 351 val rdTypes = Seq(IntRD(), VfRD()) 352 for(wbType <- wbTypes){ 353 for(rdType <- rdTypes){ 354 allRealExuParams.map { 355 case exuParam => 356 val wbPortConfigs = exuParam.wbPortConfigs 357 val wbConfigs = wbType match{ 358 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 359 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 360 case _ => None 361 } 362 val rfReadPortConfigs = exuParam.rfrPortConfigs 363 val rdConfigs = rdType match{ 364 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 365 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 366 case _ => Seq() 367 } 368 (wbConfigs, rdConfigs) 369 }.filter(_._1.isDefined) 370 .sortBy(_._1.get.priority) 371 .groupBy(_._1.get.port).map { 372 case (_, intWbRdPairs) => 373 intWbRdPairs.map(_._2).flatten 374 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 375 case (_, rdCfgs) => 376 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 377 }) 378 } 379 } 380 } 381} 382