1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.fpu.FpPipedFuncUnit 10import yunsuan.{VfmaType, VfpuType} 11import yunsuan.fpu.FloatFMA 12 13class FMA(cfg: FuConfig)(implicit p: Parameters) extends FpPipedFuncUnit(cfg) { 14 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "fma OpType not supported") 15 16 // io alias 17 private val opcode = fuOpType(3, 0) 18 private val src0 = inData.src(0) 19 private val src1 = inData.src(1) 20 private val src2 = inData.src(2) 21 22 // modules 23 private val fma = Module(new FloatFMA) 24 25 val fp_aIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src0.head(32).andR || 26 fp_fmt === VSew.e16 && !src0.head(48).andR 27 val fp_bIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src1.head(32).andR || 28 fp_fmt === VSew.e16 && !src1.head(48).andR 29 val fp_cIsFpCanonicalNAN = !(opcode === VfmaType.vfmul) && (fp_fmt === VSew.e32 && !src2.head(32).andR || 30 fp_fmt === VSew.e16 && !src2.head(48).andR) 31 32 fma.io.fire := io.in.valid 33 fma.io.fp_a := src0 34 fma.io.fp_b := src1 35 fma.io.fp_c := src2 36 fma.io.round_mode := rm 37 fma.io.fp_format := fp_fmt 38 fma.io.op_code := opcode 39 fma.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN 40 fma.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN 41 fma.io.fp_cIsFpCanonicalNAN := fp_cIsFpCanonicalNAN 42 43 private val resultData = fma.io.fp_result 44 private val fflagsData = fma.io.fflags 45 46 io.out.bits.res.fflags.get := fflagsData 47 io.out.bits.res.data := resultData 48} 49