1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.backend.fu.NewCSR._ 32import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp, Pbmt} 33import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 34 35class StoreUnit(implicit p: Parameters) extends XSModule 36 with HasDCacheParameters 37 with HasVLSUParameters 38 { 39 val io = IO(new Bundle() { 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val csrCtrl = Flipped(new CustomCSRCtrlIO) 42 val stin = Flipped(Decoupled(new MemExuInput)) 43 val issue = Valid(new MemExuInput) 44 // misalignBuffer issue path 45 val misalign_stin = Flipped(Decoupled(new LsPipelineBundle)) 46 val misalign_stout = Valid(new SqWriteBundle) 47 val tlb = new TlbRequestIO() 48 val dcache = new DCacheStoreIO 49 val pmp = Flipped(new PMPRespBundle()) 50 val lsq = ValidIO(new LsPipelineBundle) 51 val lsq_replenish = Output(new LsPipelineBundle()) 52 val feedback_slow = ValidIO(new RSFeedback) 53 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 54 // provide prefetch info to sms 55 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 56 // speculative for gated control 57 val s1_prefetch_spec = Output(Bool()) 58 val s2_prefetch_spec = Output(Bool()) 59 val stld_nuke_query = Valid(new StoreNukeQueryIO) 60 val stout = DecoupledIO(new MemExuOutput) // writeback store 61 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 62 // store mask, send to sq in store_s0 63 val st_mask_out = Valid(new StoreMaskBundle) 64 val debug_ls = Output(new DebugLsInfoBundle) 65 // vector 66 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 67 val vec_isFirstIssue = Input(Bool()) 68 // writeback to misalign buffer 69 val misalign_buf = Decoupled(new LsPipelineBundle) 70 // trigger 71 val fromCsrTrigger = Input(new CsrTriggerBundle) 72 73 val s0_s1_valid = Output(Bool()) 74 }) 75 76 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 77 78 // Pipeline 79 // -------------------------------------------------------------------------------- 80 // stage 0 81 // -------------------------------------------------------------------------------- 82 // generate addr, use addr to query DCache and DTLB 83 val s0_iss_valid = io.stin.valid 84 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 85 val s0_vec_valid = io.vecstin.valid 86 val s0_ma_st_valid = io.misalign_stin.valid 87 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid || s0_ma_st_valid 88 val s0_use_flow_ma = s0_ma_st_valid 89 val s0_use_flow_vec = s0_vec_valid && !s0_ma_st_valid 90 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 91 val s0_use_flow_prf = s0_prf_valid && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 92 val s0_use_non_prf_flow = s0_use_flow_rs || s0_use_flow_vec || s0_use_flow_ma 93 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 94 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 95 val s0_uop = Mux( 96 s0_use_flow_ma, 97 io.misalign_stin.bits.uop, 98 Mux( 99 s0_use_flow_rs, 100 s0_stin.uop, 101 s0_vecstin.uop 102 ) 103 ) 104 val s0_isFirstIssue = Mux( 105 s0_use_flow_ma, 106 false.B, 107 s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 108 ) 109 val s0_size = Mux(s0_use_non_prf_flow, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 110 val s0_mem_idx = Mux(s0_use_non_prf_flow, s0_uop.sqIdx.value, 0.U) 111 val s0_rob_idx = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 112 val s0_pc = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U) 113 val s0_instr_type = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 114 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 115 val s0_out = Wire(new LsPipelineBundle) 116 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 117 val s0_can_go = s1_ready 118 val s0_fire = s0_valid && !s0_kill && s0_can_go 119 val s0_is128bit = Wire(Bool()) 120 // vector 121 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 122 // val s0_flowPtr = s0_vecstin.flowPtr 123 // val s0_isLastElem = s0_vecstin.isLastElem 124 val s0_secondInv = s0_vecstin.usSecondInv 125 val s0_elemIdx = s0_vecstin.elemIdx 126 val s0_alignedType = s0_vecstin.alignedType 127 val s0_mBIndex = s0_vecstin.mBIndex 128 val s0_vecBaseVaddr = s0_vecstin.basevaddr 129 val s0_isFinalSplit = io.misalign_stin.valid && io.misalign_stin.bits.isFinalSplit 130 131 // generate addr 132 val s0_saddr = s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), VAddrBits) 133 val s0_fullva = Wire(UInt(XLEN.W)) 134 135 val s0_vaddr = Mux( 136 s0_use_flow_ma, 137 io.misalign_stin.bits.vaddr, 138 Mux( 139 s0_use_flow_rs, 140 s0_saddr, 141 Mux( 142 s0_use_flow_vec, 143 s0_vecstin.vaddr(VAddrBits - 1, 0), 144 io.prefetch_req.bits.vaddr 145 ) 146 ) 147 ) 148 149 val s0_alignTpye = Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)) 150 // exception check 151 val s0_addr_aligned = LookupTree(s0_alignTpye, List( 152 "b00".U -> true.B, //b 153 "b01".U -> (s0_vaddr(0) === 0.U), //h 154 "b10".U -> (s0_vaddr(1,0) === 0.U), //w 155 "b11".U -> (s0_vaddr(2,0) === 0.U) //d 156 )) 157 // if vector store sends 128-bit requests, its address must be 128-aligned 158 XSError(s0_use_flow_vec && s0_vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 159 160 val s0_isMisalign = Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) 161 val s0_addr_low = s0_vaddr(4, 0) 162 val s0_addr_Up_low = LookupTree(s0_alignTpye, List( 163 "b00".U -> 0.U, 164 "b01".U -> 1.U, 165 "b10".U -> 3.U, 166 "b11".U -> 7.U 167 )) + s0_addr_low 168 val s0_rs_corss16Bytes = s0_addr_Up_low(4) =/= s0_addr_low(4) 169 val s0_misalignWith16Byte = !s0_rs_corss16Bytes && !s0_addr_aligned && !s0_use_flow_prf 170 s0_is128bit := Mux(s0_use_flow_ma, io.misalign_stin.bits.is128bit, is128Bit(s0_vecstin.alignedType) || s0_misalignWith16Byte) 171 172 s0_fullva := Mux( 173 s0_use_flow_rs, 174 s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), XLEN), 175 Mux( 176 s0_use_flow_vec, 177 s0_vecstin.vaddr, 178 s0_vaddr 179 ) 180 ) 181 182 val s0_mask = Mux( 183 s0_use_flow_ma, 184 io.misalign_stin.bits.mask, 185 Mux( 186 s0_use_flow_rs, 187 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 188 Mux( 189 s0_use_flow_vec, 190 s0_vecstin.mask, 191 // -1.asSInt.asUInt 192 Fill(VLEN/8, 1.U(1.W)) 193 ) 194 ) 195 ) 196 197 io.tlb.req.valid := s0_valid 198 io.tlb.req.bits.vaddr := s0_vaddr 199 io.tlb.req.bits.fullva := s0_fullva 200 io.tlb.req.bits.checkfullva := s0_use_flow_rs || s0_use_flow_vec 201 io.tlb.req.bits.cmd := TlbCmd.write 202 io.tlb.req.bits.isPrefetch := s0_use_flow_prf 203 io.tlb.req.bits.size := s0_size 204 io.tlb.req.bits.kill := false.B 205 io.tlb.req.bits.memidx.is_ld := false.B 206 io.tlb.req.bits.memidx.is_st := true.B 207 io.tlb.req.bits.memidx.idx := s0_mem_idx 208 io.tlb.req.bits.debug.robIdx := s0_rob_idx 209 io.tlb.req.bits.no_translate := false.B 210 io.tlb.req.bits.debug.pc := s0_pc 211 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 212 io.tlb.req_kill := false.B 213 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 214 io.tlb.req.bits.hlvx := false.B 215 io.tlb.req.bits.pmp_addr := DontCare 216 217 // Dcache access here: not **real** dcache write 218 // just read meta and tag in dcache, to find out the store will hit or miss 219 220 // NOTE: The store request does not wait for the dcache to be ready. 221 // If the dcache is not ready at this time, the dcache is not queried. 222 // But, store prefetch request will always wait for dcache to be ready to make progress. 223 io.dcache.req.valid := s0_fire 224 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 225 io.dcache.req.bits.vaddr := s0_vaddr 226 io.dcache.req.bits.instrtype := s0_instr_type 227 228 s0_out := DontCare 229 s0_out.vaddr := s0_vaddr 230 s0_out.fullva := s0_fullva 231 // Now data use its own io 232 s0_out.data := s0_stin.src(1) 233 s0_out.uop := s0_uop 234 s0_out.miss := false.B 235 // For unaligned, we need to generate a base-aligned mask in storeunit and then do a shift split in StoreQueue. 236 s0_out.mask := Mux(s0_rs_corss16Bytes && !s0_addr_aligned, genBasemask(s0_saddr,s0_alignTpye(1,0)), s0_mask) 237 s0_out.isFirstIssue := s0_isFirstIssue 238 s0_out.isHWPrefetch := s0_use_flow_prf 239 s0_out.wlineflag := s0_wlineflag 240 s0_out.isvec := s0_use_flow_vec 241 s0_out.is128bit := s0_is128bit 242 s0_out.vecActive := s0_vecActive 243 s0_out.usSecondInv := s0_secondInv 244 s0_out.elemIdx := s0_elemIdx 245 s0_out.alignedType := s0_alignedType 246 s0_out.mbIndex := s0_mBIndex 247 s0_out.misalignWith16Byte := s0_misalignWith16Byte 248 s0_out.isMisalign := s0_isMisalign 249 s0_out.vecBaseVaddr := s0_vecBaseVaddr 250 when(s0_valid && s0_isFirstIssue) { 251 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 252 } 253 s0_out.isFrmMisAlignBuf := s0_use_flow_ma 254 s0_out.isFinalSplit := s0_isFinalSplit 255// s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) && !s0_misalignWith16Byte 256 257 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 258 io.st_mask_out.bits.mask := s0_out.mask 259 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 260 261 io.stin.ready := s1_ready && s0_use_flow_rs 262 io.vecstin.ready := s1_ready && s0_use_flow_vec 263 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 264 io.misalign_stin.ready := s1_ready && s0_use_flow_ma 265 266 // Pipeline 267 // -------------------------------------------------------------------------------- 268 // stage 1 269 // -------------------------------------------------------------------------------- 270 // TLB resp (send paddr to dcache) 271 val s1_valid = RegInit(false.B) 272 val s1_in = RegEnable(s0_out, s0_fire) 273 val s1_out = Wire(new LsPipelineBundle) 274 val s1_kill = Wire(Bool()) 275 val s1_can_go = s2_ready 276 val s1_fire = s1_valid && !s1_kill && s1_can_go 277 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 278 val s1_frm_mabuf = s1_in.isFrmMisAlignBuf 279 val s1_is128bit = s1_in.is128bit 280 281 // mmio cbo decoder 282 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 283 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 284 s1_in.uop.fuOpType === LSUOpType.cbo_inval 285 val s1_vaNeedExt = io.tlb.resp.bits.excp(0).vaNeedExt 286 val s1_isHyper = io.tlb.resp.bits.excp(0).isHyper 287 val s1_paddr = io.tlb.resp.bits.paddr(0) 288 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 289 val s1_fullva = io.tlb.resp.bits.fullva 290 val s1_isForVSnonLeafPTE = io.tlb.resp.bits.isForVSnonLeafPTE 291 val s1_tlb_miss = io.tlb.resp.bits.miss && io.tlb.resp.valid && s1_valid 292 val s1_mmio = s1_mmio_cbo 293 val s1_pbmt = Mux(!s1_tlb_miss, io.tlb.resp.bits.pbmt.head, 0.U(Pbmt.width.W)) 294 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 295 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 296 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 297 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec && !s1_frm_mabuf) 298 299 s1_ready := !s1_valid || s1_kill || s2_ready 300 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 301 when (s0_fire) { s1_valid := true.B } 302 .elsewhen (s1_fire) { s1_valid := false.B } 303 .elsewhen (s1_kill) { s1_valid := false.B } 304 305 // st-ld violation dectect request. 306 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_frm_mabuf 307 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 308 io.stld_nuke_query.bits.paddr := s1_paddr 309 io.stld_nuke_query.bits.mask := s1_in.mask 310 io.stld_nuke_query.bits.matchLine := (s1_in.isvec || s1_in.misalignWith16Byte) && s1_in.is128bit 311 312 // issue 313 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec && !s1_frm_mabuf 314 io.issue.bits := RegEnable(s0_stin, s0_valid) 315 316 // trigger 317 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 318 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 319 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 320 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 321 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 322 storeTrigger.io.fromLoadStore.vaddr := s1_in.vaddr 323 storeTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 324 storeTrigger.io.fromLoadStore.mask := s1_in.mask 325 326 val s1_trigger_action = storeTrigger.io.toLoadStore.triggerAction 327 val s1_trigger_debug_mode = TriggerAction.isDmode(s1_trigger_action) 328 val s1_trigger_breakpoint = TriggerAction.isExp(s1_trigger_action) 329 330 // goto misalignBuffer 331 val toMisalignBufferValid = s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && s1_in.isMisalign && !s1_in.misalignWith16Byte && !s1_trigger_breakpoint && !s1_trigger_debug_mode 332 io.misalign_buf.valid := toMisalignBufferValid 333 io.misalign_buf.bits := io.lsq.bits 334 val misalignBufferNack = toMisalignBufferValid && !io.misalign_buf.ready 335 336 // for misalign in vsMergeBuffer 337 io.s0_s1_valid := s0_valid || s1_valid 338 339 // Send TLB feedback to store issue queue 340 // Store feedback is generated in store_s1, sent to RS in store_s2 341 val s1_feedback = Wire(Valid(new RSFeedback)) 342 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 343 s1_feedback.bits.hit := !s1_tlb_miss && !misalignBufferNack 344 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 345 s1_feedback.bits.robIdx := s1_out.uop.robIdx 346 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 347 s1_feedback.bits.dataInvalidSqIdx := DontCare 348 s1_feedback.bits.sqIdx := s1_out.uop.sqIdx 349 s1_feedback.bits.lqIdx := s1_out.uop.lqIdx 350 351 XSDebug(s1_feedback.valid, 352 "S1 Store: tlbHit: %d robIdx: %d\n", 353 s1_feedback.bits.hit, 354 s1_feedback.bits.robIdx.value 355 ) 356 357 // io.feedback_slow := s1_feedback 358 359 // get paddr from dtlb, check if rollback is needed 360 // writeback store inst to lsq 361 s1_out := s1_in 362 s1_out.paddr := s1_paddr 363 s1_out.gpaddr := s1_gpaddr 364 s1_out.fullva := s1_fullva 365 s1_out.vaNeedExt := s1_vaNeedExt 366 s1_out.isHyper := s1_isHyper 367 s1_out.miss := false.B 368 s1_out.nc := Pbmt.isNC(s1_pbmt) 369 s1_out.mmio := s1_mmio || Pbmt.isIO(s1_pbmt) 370 s1_out.tlbMiss := s1_tlb_miss 371 s1_out.atomic := s1_mmio || Pbmt.isIO(s1_pbmt) 372 s1_out.isForVSnonLeafPTE := s1_isForVSnonLeafPTE 373 when (RegNext(io.tlb.req.bits.checkfullva) && 374 (s1_out.uop.exceptionVec(storePageFault) || 375 s1_out.uop.exceptionVec(storeAccessFault) || 376 s1_out.uop.exceptionVec(storeGuestPageFault))) { 377 s1_out.uop.exceptionVec(storeAddrMisaligned) := false.B 378 } 379 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 380 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 381 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 382 383 s1_out.uop.flushPipe := false.B 384 s1_out.uop.trigger := s1_trigger_action 385 s1_out.uop.exceptionVec(breakPoint) := s1_trigger_breakpoint 386 s1_out.uop.exceptionVec(storeAddrMisaligned) := s1_mmio && s1_in.isMisalign 387 s1_out.vecVaddrOffset := Mux( 388 s1_trigger_debug_mode || s1_trigger_breakpoint, 389 storeTrigger.io.toLoadStore.triggerVaddr - s1_in.vecBaseVaddr, 390 s1_in.vaddr + genVFirstUnmask(s1_in.mask).asUInt - s1_in.vecBaseVaddr , 391 ) 392 s1_out.vecTriggerMask := Mux(s1_trigger_debug_mode || s1_trigger_breakpoint, storeTrigger.io.toLoadStore.triggerMask, 0.U) 393 394 // scalar store and scalar load nuke check, and also other purposes 395 //A 128-bit aligned unaligned memory access requires changing the unaligned flag bit in sq 396 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 397 io.lsq.bits := s1_out 398 io.lsq.bits.miss := s1_tlb_miss 399 io.lsq.bits.updateAddrValid := (!s1_in.isMisalign || s1_in.misalignWith16Byte) && (!s1_frm_mabuf || s1_in.isFinalSplit) || s1_exception 400 // kill dcache write intent request when tlb miss or exception 401 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 402 io.dcache.s1_paddr := s1_paddr 403 404 // write below io.out.bits assign sentence to prevent overwriting values 405 val s1_tlb_memidx = io.tlb.resp.bits.memidx 406 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 407 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 408 s1_out.uop.debugInfo.tlbRespTime := GTimer() 409 } 410 411 // Pipeline 412 // -------------------------------------------------------------------------------- 413 // stage 2 414 // -------------------------------------------------------------------------------- 415 // mmio check 416 val s2_valid = RegInit(false.B) 417 val s2_in = RegEnable(s1_out, s1_fire) 418 val s2_out = Wire(new LsPipelineBundle) 419 val s2_kill = Wire(Bool()) 420 val s2_can_go = s3_ready 421 val s2_fire = s2_valid && !s2_kill && s2_can_go 422 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 423 val s2_frm_mabuf = s2_in.isFrmMisAlignBuf 424 val s2_pbmt = RegEnable(s1_pbmt, s1_fire) 425 val s2_trigger_debug_mode = RegEnable(s1_trigger_debug_mode, false.B, s1_fire) 426 val s2_mis_align = RegEnable(toMisalignBufferValid, s1_fire) 427 428 s2_ready := !s2_valid || s2_kill || s3_ready 429 when (s1_fire) { s2_valid := true.B } 430 .elsewhen (s2_fire) { s2_valid := false.B } 431 .elsewhen (s2_kill) { s2_valid := false.B } 432 433 val s2_pmp = WireInit(io.pmp) 434 435 val s2_exception = RegNext(s1_feedback.bits.hit) && 436 (s2_trigger_debug_mode || ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) 437 val s2_mmio = (s2_in.mmio || (Pbmt.isPMA(s2_pbmt) && s2_pmp.mmio)) && RegNext(s1_feedback.bits.hit) 438 val s2_actually_uncache = (Pbmt.isPMA(s2_pbmt) && s2_pmp.mmio || s2_in.nc || s2_in.mmio) && RegNext(s1_feedback.bits.hit) 439 val s2_uncache = !s2_exception && !s2_in.tlbMiss && s2_actually_uncache 440 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect) 441 442 s2_out := s2_in 443 s2_out.af := s2_out.uop.exceptionVec(storeAccessFault) 444 s2_out.mmio := s2_mmio && !s2_exception 445 s2_out.atomic := s2_in.atomic || Pbmt.isPMA(s2_pbmt) && s2_pmp.atomic 446 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || 447 s2_pmp.st || 448 ((s2_in.isvec || s2_frm_mabuf) && s2_actually_uncache && RegNext(s1_feedback.bits.hit)) 449 ) && s2_vecActive 450 s2_out.uop.exceptionVec(storeAddrMisaligned) := s2_mmio && s2_in.isMisalign 451 s2_out.uop.vpu.vstart := s2_in.vecVaddrOffset >> s2_in.uop.vpu.veew 452 453 // kill dcache write intent request when mmio or exception 454 io.dcache.s2_kill := (s2_uncache || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 455 io.dcache.s2_pc := s2_out.uop.pc 456 // TODO: dcache resp 457 io.dcache.resp.ready := true.B 458 459 // feedback tlb miss to RS in store_s2 460 val feedback_slow_valid = WireInit(false.B) 461 feedback_slow_valid := s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect) && !s1_out.isvec && !s1_frm_mabuf 462 io.feedback_slow.valid := GatedValidRegNext(feedback_slow_valid) 463 io.feedback_slow.bits := RegEnable(s1_feedback.bits, feedback_slow_valid) 464 465 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit && s1_feedback.valid) && s2_in.isvec 466 467 val s2_misalign_stout = WireInit(0.U.asTypeOf(io.misalign_stout)) 468 s2_misalign_stout.valid := s2_valid && s2_can_go && s2_frm_mabuf 469 s2_misalign_stout.bits.mmio := s2_out.mmio 470 s2_misalign_stout.bits.vaddr := s2_out.vaddr 471 s2_misalign_stout.bits.isHyper := s2_out.isHyper 472 s2_misalign_stout.bits.paddr := s2_out.paddr 473 s2_misalign_stout.bits.gpaddr := s2_out.gpaddr 474 s2_misalign_stout.bits.isForVSnonLeafPTE := s2_out.isForVSnonLeafPTE 475 s2_misalign_stout.bits.need_rep := RegEnable(s1_tlb_miss, s1_fire) 476 s2_misalign_stout.bits.uop.exceptionVec := s2_out.uop.exceptionVec 477 io.misalign_stout := s2_misalign_stout 478 479 // mmio and exception 480 io.lsq_replenish := s2_out 481 io.lsq_replenish.af := s2_out.af && s2_valid && !s2_kill 482 483 // prefetch related 484 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 485 io.lsq_replenish.updateAddrValid := (!s2_out.isMisalign || s2_out.misalignWith16Byte) && (!s2_frm_mabuf || s2_out.isFinalSplit) || s2_exception 486 487 // RegNext prefetch train for better timing 488 // ** Now, prefetch train is valid at store s3 ** 489 val s2_prefetch_train_valid = WireInit(false.B) 490 s2_prefetch_train_valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_out.nc && !s2_in.tlbMiss && !s2_in.isHWPrefetch 491 if(EnableStorePrefetchSMS) { 492 io.s1_prefetch_spec := s1_fire 493 io.s2_prefetch_spec := s2_prefetch_train_valid 494 io.prefetch_train.valid := RegNext(s2_prefetch_train_valid) 495 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = s2_prefetch_train_valid) 496 }else { 497 io.s1_prefetch_spec := false.B 498 io.s2_prefetch_spec := false.B 499 io.prefetch_train.valid := false.B 500 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = false.B) 501 } 502 // override miss bit 503 io.prefetch_train.bits.miss := RegEnable(io.dcache.resp.bits.miss, s2_prefetch_train_valid) 504 // TODO: add prefetch and access bit 505 io.prefetch_train.bits.meta_prefetch := false.B 506 io.prefetch_train.bits.meta_access := false.B 507 io.prefetch_train.bits.isFinalSplit := false.B 508 io.prefetch_train.bits.misalignWith16Byte := false.B 509 io.prefetch_train.bits.isMisalign := false.B 510 io.prefetch_train.bits.misalignNeedWakeUp := false.B 511 io.prefetch_train.bits.updateAddrValid := false.B 512 513 // Pipeline 514 // -------------------------------------------------------------------------------- 515 // stage 3 516 // -------------------------------------------------------------------------------- 517 // store write back 518 val s3_valid = RegInit(false.B) 519 val s3_in = RegEnable(s2_out, s2_fire) 520 val s3_out = Wire(new MemExuOutput(isVector = true)) 521 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 522 val s3_can_go = s3_ready 523 val s3_fire = s3_valid && !s3_kill && s3_can_go 524 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 525 526 // store misalign will not writeback to rob now 527 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch && !s2_mis_align && !s2_frm_mabuf } 528 .elsewhen (s3_fire) { s3_valid := false.B } 529 .elsewhen (s3_kill) { s3_valid := false.B } 530 531 // wb: writeback 532 val SelectGroupSize = RollbackGroupSize 533 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 534 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 535 536 s3_out := DontCare 537 s3_out.uop := s3_in.uop 538 s3_out.data := DontCare 539 s3_out.debug.isMMIO := s3_in.mmio 540 s3_out.debug.isNC := s3_in.nc 541 s3_out.debug.paddr := s3_in.paddr 542 s3_out.debug.vaddr := s3_in.vaddr 543 s3_out.debug.isPerfCnt := false.B 544 545 // Pipeline 546 // -------------------------------------------------------------------------------- 547 // stage x 548 // -------------------------------------------------------------------------------- 549 // delay TotalSelectCycles - 2 cycle(s) 550 val TotalDelayCycles = TotalSelectCycles - 2 551 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 552 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 553 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 554 val sx_in_vec = Wire(Vec(TotalDelayCycles +1, Bool())) 555 556 // backward ready signal 557 s3_ready := sx_ready.head 558 for (i <- 0 until TotalDelayCycles + 1) { 559 if (i == 0) { 560 sx_valid(i) := s3_valid 561 sx_in(i).output := s3_out 562 sx_in(i).vecFeedback := s3_vecFeedback 563 sx_in(i).nc := s3_in.nc 564 sx_in(i).mmio := s3_in.mmio 565 sx_in(i).usSecondInv := s3_in.usSecondInv 566 sx_in(i).elemIdx := s3_in.elemIdx 567 sx_in(i).alignedType := s3_in.alignedType 568 sx_in(i).mbIndex := s3_in.mbIndex 569 sx_in(i).mask := s3_in.mask 570 sx_in(i).vaddr := s3_in.fullva 571 sx_in(i).vaNeedExt := s3_in.vaNeedExt 572 sx_in(i).gpaddr := s3_in.gpaddr 573 sx_in(i).isForVSnonLeafPTE := s3_in.isForVSnonLeafPTE 574 sx_in(i).vecTriggerMask := s3_in.vecTriggerMask 575 sx_in_vec(i) := s3_in.isvec 576 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 577 } else { 578 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 579 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 580 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 581 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 582 583 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 584 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 585 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 586 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 587 sx_in_vec(i) := RegEnable(sx_in_vec(i-1), prev_fire) 588 } 589 } 590 val sx_last_valid = sx_valid.takeRight(1).head 591 val sx_last_ready = sx_ready.takeRight(1).head 592 val sx_last_in = sx_in.takeRight(1).head 593 val sx_last_in_vec = sx_in_vec.takeRight(1).head 594 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 595 596 // write back: normal store, nc store 597 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && !sx_last_in_vec //isStore(sx_last_in.output.uop.fuType) 598 io.stout.bits := sx_last_in.output 599 io.stout.bits.uop.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, StaCfg) 600 601 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && sx_last_in_vec //isVStore(sx_last_in.output.uop.fuType) 602 // TODO: implement it! 603 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 604 io.vecstout.bits.hit := sx_last_in.vecFeedback 605 io.vecstout.bits.isvec := true.B 606 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 607 io.vecstout.bits.flushState := DontCare 608 io.vecstout.bits.trigger := sx_last_in.output.uop.trigger 609 io.vecstout.bits.nc := sx_last_in.nc 610 io.vecstout.bits.mmio := sx_last_in.mmio 611 io.vecstout.bits.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, VstuCfg) 612 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 613 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 614 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 615 io.vecstout.bits.alignedType := sx_last_in.alignedType 616 io.vecstout.bits.mask := sx_last_in.mask 617 io.vecstout.bits.vaddr := sx_last_in.vaddr 618 io.vecstout.bits.vaNeedExt := sx_last_in.vaNeedExt 619 io.vecstout.bits.gpaddr := sx_last_in.gpaddr 620 io.vecstout.bits.isForVSnonLeafPTE := sx_last_in.isForVSnonLeafPTE 621 io.vecstout.bits.vstart := sx_last_in.output.uop.vpu.vstart 622 io.vecstout.bits.vecTriggerMask := sx_last_in.vecTriggerMask 623 // io.vecstout.bits.reg_offset.map(_ := DontCare) 624 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 625 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 626 // io.vecstout.bits.vecdata.map(_ := DontCare) 627 // io.vecstout.bits.mask.map(_ := DontCare) 628 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 629 630 io.debug_ls := DontCare 631 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 632 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 633 634 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 635 XSDebug(cond, 636 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 637 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 638 p"op ${Binary(pipeline.uop.fuOpType)} " + 639 p"data ${Hexadecimal(pipeline.data)} " + 640 p"mask ${Hexadecimal(pipeline.mask)}\n" 641 ) 642 } 643 644 printPipeLine(s0_out, s0_valid, "S0") 645 printPipeLine(s1_out, s1_valid, "S1") 646 647 // perf cnt 648 XSPerfAccumulate("s0_in_valid", s0_valid) 649 XSPerfAccumulate("s0_in_fire", s0_fire) 650 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 651 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 652 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 653 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 654 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 655 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 656 657 XSPerfAccumulate("s1_in_valid", s1_valid) 658 XSPerfAccumulate("s1_in_fire", s1_fire) 659 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 660 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 661 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 662 // end 663} 664