1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15import xiangshan.backend.issue.EntryBundles.EntryDeqRespBundle 16 17case class IssueBlockParams( 18 // top down 19 private val exuParams: Seq[ExeUnitParams], 20 val numEntries : Int, 21 numEnq : Int, 22 numComp : Int, 23 numDeqOutside : Int = 0, 24 numWakeupFromOthers : Int = 0, 25 XLEN : Int = 64, 26 VLEN : Int = 128, 27 // calculate in scheduler 28 var idxInSchBlk : Int = 0, 29)( 30 implicit 31 val schdType: SchedulerType, 32) { 33 var backendParam: BackendParams = null 34 35 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 36 37 val allExuParams = exuParams 38 39 def updateIdx(idx: Int): Unit = { 40 this.idxInSchBlk = idx 41 } 42 43 def inMemSchd: Boolean = schdType == MemScheduler() 44 45 def inIntSchd: Boolean = schdType == IntScheduler() 46 47 def inVfSchd: Boolean = schdType == VfScheduler() 48 49 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 50 51 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 52 53 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 54 55 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 56 57 def isVecLduIQ: Boolean = inMemSchd && (VlduCnt + VseglduCnt) > 0 58 59 def isVecStuIQ: Boolean = inMemSchd && (VstuCnt + VsegstuCnt) > 0 60 61 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 62 63 def needFeedBackSqIdx: Boolean = isVecMemIQ || isStAddrIQ 64 65 def needFeedBackLqIdx: Boolean = isVecMemIQ || isLdAddrIQ 66 67 def needLoadDependency: Boolean = exuBlockParams.map(_.needLoadDependency).reduce(_ || _) 68 69 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 70 71 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 72 73 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 74 75 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 76 77 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 78 79 def numV0Src: Int = exuBlockParams.map(_.numV0Src).max 80 81 def numVlSrc: Int = exuBlockParams.map(_.numVlSrc).max 82 83 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 84 85 def numSrc: Int = exuBlockParams.map(_.numSrc).max 86 87 def readIntRf: Boolean = numIntSrc > 0 88 89 def readFpRf: Boolean = numFpSrc > 0 90 91 def readVecRf: Boolean = numVecSrc > 0 92 93 def readVfRf: Boolean = numVfSrc > 0 94 95 def readV0Rf: Boolean = numV0Src > 0 96 97 def readVlRf: Boolean = numVlSrc > 0 98 99 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 100 101 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 102 103 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 104 105 def writeV0Rf: Boolean = exuBlockParams.map(_.writeV0Rf).reduce(_ || _) 106 107 def writeVlRf: Boolean = exuBlockParams.map(_.writeVlRf).reduce(_ || _) 108 109 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 110 111 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 112 113 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 114 115 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 116 117 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 118 119 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 120 121 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 122 123 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 124 125 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 126 127 def writeVConfig: Boolean = exuBlockParams.map(_.writeVConfig).reduce(_ || _) 128 129 def writeVType: Boolean = exuBlockParams.map(_.writeVType).reduce(_ || _) 130 131 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 132 133 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 134 135 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 136 137 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 138 139 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 140 141 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 142 143 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 144 145 def numDeq: Int = numDeqOutside + exuBlockParams.length 146 147 def numSimp: Int = numEntries - numEnq - numComp 148 149 def isAllComp: Boolean = numComp == (numEntries - numEnq) 150 151 def isAllSimp: Boolean = numComp == 0 152 153 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 154 155 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 156 157 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 158 159 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 160 161 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 162 163 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 164 165 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 166 167 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 168 169 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 170 171 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 172 173 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 174 175 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 176 177 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 178 179 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 180 181 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 182 183 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 184 185 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 186 187 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 188 189 def LdExuCnt = LduCnt + HyuCnt 190 191 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 192 193 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 194 195 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 196 197 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 198 199 def VseglduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vsegldu)).sum 200 201 def VsegstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vsegstu)).sum 202 203 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 204 205 def numWriteRegCache: Int = exuBlockParams.map(x => if (x.needWriteRegCache) 1 else 0).sum 206 207 def needWriteRegCache: Boolean = numWriteRegCache > 0 208 209 def needReadRegCache: Boolean = exuBlockParams.map(_.needReadRegCache).reduce(_ || _) 210 211 def needOg2Resp: Boolean = exuBlockParams.map(_.needOg2).reduce(_ || _) 212 213 /** 214 * Get the regfile type that this issue queue need to read 215 */ 216 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 217 218 /** 219 * Get the regfile type that this issue queue need to read 220 */ 221 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 222 223 /** 224 * Get the max width of psrc 225 */ 226 def rdPregIdxWidth = { 227 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 228 } 229 230 /** 231 * Get the max width of pdest 232 */ 233 def wbPregIdxWidth = { 234 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 235 } 236 237 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 238 239 /** 240 * Get exu source wake up 241 */ 242 def wakeUpInExuSources: Seq[WakeUpSource] = { 243 exuBlockParams 244 .flatMap(_.iqWakeUpSinkPairs) 245 .map(_.source) 246 .distinctBy(_.name) 247 } 248 249 def wakeUpOutExuSources: Seq[WakeUpSource] = { 250 exuBlockParams 251 .flatMap(_.iqWakeUpSourcePairs) 252 .map(_.source) 253 .distinctBy(_.name) 254 } 255 256 def wakeUpToExuSinks = exuBlockParams 257 .flatMap(_.iqWakeUpSourcePairs) 258 .map(_.sink).distinct 259 260 def numWakeupToIQ: Int = wakeUpInExuSources.size 261 262 def numWakeupFromIQ: Int = wakeUpInExuSources.size 263 264 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 265 266 def numWakeupFromWB = { 267 val pregSet = this.pregReadSet 268 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 269 } 270 271 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 272 273 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readIntRf).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 274 275 def needWakeupFromFpWBPort = if (this.exuBlockParams.map(_.hasStdFu).reduce(_ || _)) { 276 // here add fp load WB wakeup to std 277 backendParam.allExuParams.filter(x => (!wakeUpInExuSources.map(_.name).contains(x.name) || x.hasLoadExu) && this.readFpRf).groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 278 } 279 else { 280 backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readFpRf).groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 281 } 282 283 def needWakeupFromVfWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVecRf).groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 284 285 def needWakeupFromV0WBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readV0Rf).groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 286 287 def needWakeupFromVlWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVlRf).groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 288 289 def hasWakeupFromMem: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isMemExeUnit).fold(false)(_ | _) 290 291 def hasWakeupFromVf: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isVfExeUnit).fold(false)(_ | _) 292 293 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 294 295 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 296 297 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 298 299 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 300 301 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 302 303 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 304 305 // set load imm to 32-bit for fused_lui_load 306 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 307 308 def needImm: Boolean = deqImmTypes.nonEmpty 309 310 // cfgs(exuIdx)(set of exu's wb) 311 312 /** 313 * Get [[PregWB]] of this IssueBlock 314 * @return set of [[PregWB]] of [[ExeUnit]] 315 */ 316 def getWbCfgs: Seq[Set[PregWB]] = { 317 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 318 } 319 320 def canAccept(fuType: UInt): Bool = { 321 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 322 } 323 324 def bindBackendParam(param: BackendParams): Unit = { 325 backendParam = param 326 } 327 328 def wakeUpSourceExuIdx: Seq[Int] = { 329 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 330 } 331 332 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 333 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 334 } 335 336 def genExuInputDecoupledCopySrcBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 337 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputCopySrcBundle))) 338 } 339 340 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 341 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 342 } 343 344 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 345 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 346 } 347 348 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 349 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 350 } 351 352 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 353 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 354 } 355 356 def genIssueValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIssueBundle]] = { 357 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => ValidIO(new IssueQueueIssueBundle(this, x)))) 358 } 359 360 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 361 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 362 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 363 case _ => Seq() 364 } 365 val fpBundle = schdType match { 366 case FpScheduler() | MemScheduler() => needWakeupFromFpWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 367 case _ => Seq() 368 } 369 val vfBundle = schdType match { 370 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 371 case _ => Seq() 372 } 373 val v0Bundle = schdType match { 374 case VfScheduler() | MemScheduler() => needWakeupFromV0WBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 375 case _ => Seq() 376 } 377 val vlBundle = schdType match { 378 case VfScheduler() | MemScheduler() => needWakeupFromVlWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 379 case _ => Seq() 380 } 381 MixedVec(intBundle ++ fpBundle ++ vfBundle ++ v0Bundle ++ vlBundle) 382 } 383 384 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 385 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 386 } 387 388 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 389 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 390 } 391 392 def genOGRespBundle(implicit p: Parameters) = { 393 implicit val issueBlockParams = this 394 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 395 } 396 397 def genOG2RespBundle(implicit p: Parameters) = { 398 implicit val issueBlockParams = this 399 MixedVec(exuBlockParams.map(_ => new Valid(new EntryDeqRespBundle))) 400 } 401 402 def genWbFuBusyTableWriteBundle(implicit p: Parameters) = { 403 implicit val issueBlockParams = this 404 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 405 } 406 407 def genWbFuBusyTableReadBundle(implicit p: Parameters) = { 408 implicit val issueBlockParams = this 409 MixedVec(exuBlockParams.map{ x => 410 new WbFuBusyTableReadBundle(x) 411 }) 412 } 413 414 def genWbConflictBundle()(implicit p: Parameters) = { 415 implicit val issueBlockParams = this 416 MixedVec(exuBlockParams.map { x => 417 new WbConflictBundle(x) 418 }) 419 } 420 421 def getIQName = { 422 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 423 } 424 425 def getEntryName = { 426 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 427 } 428} 429