chore(dispatch): remove useless code and files (#4288)

area(EXU): add parameter `needCopySrc` in FuConfig (#4063)

feat(backend): NewDispatch

chore: use scala-provided `distinctBy`

power(IssueQueue): add clock gate for deqDelay reg (#3583)

timing(Backend): add OG2 stage for vector mem (#3482)

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

Backend: remove useless loadCancel for fix timing (#3374)

IssueQueue: receive rcIdx from wakeup, add new data source type regcache

Backend: add reg cache data writing back path

build: purge chisel 3 and add deprecation check (#3250)

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

IssueQueueMemAddrImp: only wen signals for data types that load IQ will write back can be sent out

IssueBlockParams: check the type of read operands when generating the WB waking up ports

IssueQueue: support v0 & vl split

Backend: update all Params' signals and methods for v0 & vl split

Merge branch 'master' into vlsu-merge-master-0504

Backend: add FpScheduler

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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Backend: reduce the width of LoadDependency to 2 bits

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

IssueQueue: add vf <-> mem fast wake up

Backend: remove vf wb wakeup