1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15import xiangshan.backend.issue.EntryBundles.EntryDeqRespBundle 16 17case class IssueBlockParams( 18 // top down 19 private val exuParams: Seq[ExeUnitParams], 20 val numEntries : Int, 21 numEnq : Int, 22 numComp : Int, 23 numDeqOutside : Int = 0, 24 numWakeupFromOthers : Int = 0, 25 XLEN : Int = 64, 26 VLEN : Int = 128, 27 vaddrBits : Int = 39, 28 // calculate in scheduler 29 var idxInSchBlk : Int = 0, 30)( 31 implicit 32 val schdType: SchedulerType, 33) { 34 var backendParam: BackendParams = null 35 36 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 37 38 val allExuParams = exuParams 39 40 def updateIdx(idx: Int): Unit = { 41 this.idxInSchBlk = idx 42 } 43 44 def inMemSchd: Boolean = schdType == MemScheduler() 45 46 def inIntSchd: Boolean = schdType == IntScheduler() 47 48 def inVfSchd: Boolean = schdType == VfScheduler() 49 50 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 51 52 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 53 54 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 55 56 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 57 58 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 59 60 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 61 62 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 63 64 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 65 66 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 67 68 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 69 70 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 71 72 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 73 74 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 75 76 def numSrc: Int = exuBlockParams.map(_.numSrc).max 77 78 def readIntRf: Boolean = numIntSrc > 0 79 80 def readFpRf: Boolean = numFpSrc > 0 81 82 def readVecRf: Boolean = numVecSrc > 0 83 84 def readVfRf: Boolean = numVfSrc > 0 85 86 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 87 88 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 89 90 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 91 92 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 93 94 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 95 96 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 97 98 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 99 100 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 101 102 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 103 104 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 105 106 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 107 108 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 109 110 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 111 112 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 113 114 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 115 116 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 117 118 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 119 120 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 121 122 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 123 124 def numDeq: Int = numDeqOutside + exuBlockParams.length 125 126 def numSimp: Int = numEntries - numEnq - numComp 127 128 def isAllComp: Boolean = numComp == (numEntries - numEnq) 129 130 def isAllSimp: Boolean = numComp == 0 131 132 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 133 134 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 135 136 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 137 138 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 139 140 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 141 142 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 143 144 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 145 146 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 147 148 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 149 150 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 151 152 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 153 154 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 155 156 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 157 158 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 159 160 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 161 162 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 163 164 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 165 166 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 167 168 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 169 170 def LdExuCnt = LduCnt + HyuCnt 171 172 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 173 174 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 175 176 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 177 178 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 179 180 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 181 182 /** 183 * Get the regfile type that this issue queue need to read 184 */ 185 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 186 187 /** 188 * Get the regfile type that this issue queue need to read 189 */ 190 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 191 192 /** 193 * Get the max width of psrc 194 */ 195 def rdPregIdxWidth = { 196 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 197 } 198 199 /** 200 * Get the max width of pdest 201 */ 202 def wbPregIdxWidth = { 203 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 204 } 205 206 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 207 208 /** Get exu source wake up 209 * @todo replace with 210 * exuBlockParams 211 * .flatMap(_.iqWakeUpSinkPairs) 212 * .map(_.source) 213 * .distinctBy(_.name) 214 * when xiangshan is updated to 2.13.11 215 */ 216 def wakeUpInExuSources: Seq[WakeUpSource] = { 217 SeqUtils.distinctBy( 218 exuBlockParams 219 .flatMap(_.iqWakeUpSinkPairs) 220 .map(_.source) 221 )(_.name) 222 } 223 224 def wakeUpOutExuSources: Seq[WakeUpSource] = { 225 SeqUtils.distinctBy( 226 exuBlockParams 227 .flatMap(_.iqWakeUpSourcePairs) 228 .map(_.source) 229 )(_.name) 230 } 231 232 def wakeUpToExuSinks = exuBlockParams 233 .flatMap(_.iqWakeUpSourcePairs) 234 .map(_.sink).distinct 235 236 def numWakeupToIQ: Int = wakeUpInExuSources.size 237 238 def numWakeupFromIQ: Int = wakeUpInExuSources.size 239 240 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 241 242 def numWakeupFromWB = { 243 val pregSet = this.pregReadSet 244 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 245 } 246 247 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 248 249 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 250 251 def needWakeupFromVfWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 252 253 def hasWakeupFromMem: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isMemExeUnit).fold(false)(_ | _) 254 255 def hasWakeupFromVf: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isVfExeUnit).fold(false)(_ | _) 256 257 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 258 259 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 260 261 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 262 263 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 264 265 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 266 267 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 268 269 // set load imm to 32-bit for fused_lui_load 270 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 271 272 def needImm: Boolean = deqImmTypes.nonEmpty 273 274 // cfgs(exuIdx)(set of exu's wb) 275 276 /** 277 * Get [[PregWB]] of this IssueBlock 278 * @return set of [[PregWB]] of [[ExeUnit]] 279 */ 280 def getWbCfgs: Seq[Set[PregWB]] = { 281 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 282 } 283 284 def canAccept(fuType: UInt): Bool = { 285 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 286 } 287 288 def bindBackendParam(param: BackendParams): Unit = { 289 backendParam = param 290 } 291 292 def wakeUpSourceExuIdx: Seq[Int] = { 293 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 294 } 295 296 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 297 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 298 } 299 300 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 301 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 302 } 303 304 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 305 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 306 } 307 308 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 309 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 310 } 311 312 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 313 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 314 } 315 316 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 317 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 318 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 319 case _ => Seq() 320 } 321 val vfBundle = schdType match { 322 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 323 case _ => Seq() 324 } 325 MixedVec(intBundle ++ vfBundle) 326 } 327 328 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 329 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 330 } 331 332 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 333 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 334 } 335 336 def genOGRespBundle(implicit p: Parameters) = { 337 implicit val issueBlockParams = this 338 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 339 } 340 341 def genOG2RespBundle(implicit p: Parameters) = { 342 implicit val issueBlockParams = this 343 MixedVec(exuBlockParams.map(_ => new Valid(new EntryDeqRespBundle))) 344 } 345 346 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 347 implicit val issueBlockParams = this 348 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 349 } 350 351 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 352 implicit val issueBlockParams = this 353 MixedVec(exuBlockParams.map{ x => 354 new WbFuBusyTableReadBundle(x) 355 }) 356 } 357 358 def genWbConflictBundle()(implicit p: Parameters) = { 359 implicit val issueBlockParams = this 360 MixedVec(exuBlockParams.map { x => 361 new WbConflictBundle(x) 362 }) 363 } 364 365 def getIQName = { 366 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 367 } 368 369 def getEntryName = { 370 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 371 } 372} 373