1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15 16case class IssueBlockParams( 17 // top down 18 private val exuParams: Seq[ExeUnitParams], 19 val numEntries : Int, 20 numEnq : Int, 21 numComp : Int, 22 numDeqOutside : Int = 0, 23 numWakeupFromOthers : Int = 0, 24 XLEN : Int = 64, 25 VLEN : Int = 128, 26 vaddrBits : Int = 39, 27 // calculate in scheduler 28 var idxInSchBlk : Int = 0, 29)( 30 implicit 31 val schdType: SchedulerType, 32) { 33 var backendParam: BackendParams = null 34 35 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 36 37 val allExuParams = exuParams 38 39 def updateIdx(idx: Int): Unit = { 40 this.idxInSchBlk = idx 41 } 42 43 def inMemSchd: Boolean = schdType == MemScheduler() 44 45 def inIntSchd: Boolean = schdType == IntScheduler() 46 47 def inVfSchd: Boolean = schdType == VfScheduler() 48 49 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 50 51 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 52 53 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 54 55 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 56 57 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 58 59 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 60 61 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 62 63 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 64 65 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 66 67 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 68 69 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 70 71 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 72 73 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 74 75 def numSrc: Int = exuBlockParams.map(_.numSrc).max 76 77 def readIntRf: Boolean = numIntSrc > 0 78 79 def readFpRf: Boolean = numFpSrc > 0 80 81 def readVecRf: Boolean = numVecSrc > 0 82 83 def readVfRf: Boolean = numVfSrc > 0 84 85 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 86 87 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 88 89 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 90 91 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 92 93 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 94 95 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 96 97 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 98 99 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 100 101 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 102 103 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 104 105 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 106 107 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 108 109 def writeVConfig: Boolean = exuBlockParams.map(_.writeVConfig).reduce(_ || _) 110 111 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 112 113 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 114 115 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 116 117 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 118 119 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 120 121 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 122 123 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 124 125 def numDeq: Int = numDeqOutside + exuBlockParams.length 126 127 def numSimp: Int = numEntries - numEnq - numComp 128 129 def isAllComp: Boolean = numComp == (numEntries - numEnq) 130 131 def isAllSimp: Boolean = numComp == 0 132 133 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 134 135 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 136 137 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 138 139 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 140 141 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 142 143 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 144 145 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 146 147 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 148 149 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 150 151 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 152 153 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 154 155 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 156 157 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 158 159 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 160 161 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 162 163 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 164 165 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 166 167 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 168 169 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 170 171 def LdExuCnt = LduCnt + HyuCnt 172 173 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 174 175 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 176 177 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 178 179 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 180 181 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 182 183 /** 184 * Get the regfile type that this issue queue need to read 185 */ 186 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 187 188 /** 189 * Get the regfile type that this issue queue need to read 190 */ 191 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 192 193 /** 194 * Get the max width of psrc 195 */ 196 def rdPregIdxWidth = { 197 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 198 } 199 200 /** 201 * Get the max width of pdest 202 */ 203 def wbPregIdxWidth = { 204 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 205 } 206 207 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 208 209 /** Get exu source wake up 210 * @todo replace with 211 * exuBlockParams 212 * .flatMap(_.iqWakeUpSinkPairs) 213 * .map(_.source) 214 * .distinctBy(_.name) 215 * when xiangshan is updated to 2.13.11 216 */ 217 def wakeUpInExuSources: Seq[WakeUpSource] = { 218 SeqUtils.distinctBy( 219 exuBlockParams 220 .flatMap(_.iqWakeUpSinkPairs) 221 .map(_.source) 222 )(_.name) 223 } 224 225 def wakeUpOutExuSources: Seq[WakeUpSource] = { 226 SeqUtils.distinctBy( 227 exuBlockParams 228 .flatMap(_.iqWakeUpSourcePairs) 229 .map(_.source) 230 )(_.name) 231 } 232 233 def wakeUpToExuSinks = exuBlockParams 234 .flatMap(_.iqWakeUpSourcePairs) 235 .map(_.sink).distinct 236 237 def numWakeupToIQ: Int = wakeUpInExuSources.size 238 239 def numWakeupFromIQ: Int = wakeUpInExuSources.size 240 241 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 242 243 def numWakeupFromWB = { 244 val pregSet = this.pregReadSet 245 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 246 } 247 248 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 249 250 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 251 252 def needWakeupFromVfWBPort = backendParam.allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 253 254 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 255 256 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 257 258 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 259 260 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 261 262 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 263 264 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 265 266 // set load imm to 32-bit for fused_lui_load 267 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 268 269 def needImm: Boolean = deqImmTypes.nonEmpty 270 271 // cfgs(exuIdx)(set of exu's wb) 272 273 /** 274 * Get [[PregWB]] of this IssueBlock 275 * @return set of [[PregWB]] of [[ExeUnit]] 276 */ 277 def getWbCfgs: Seq[Set[PregWB]] = { 278 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 279 } 280 281 def canAccept(fuType: UInt): Bool = { 282 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 283 } 284 285 def bindBackendParam(param: BackendParams): Unit = { 286 backendParam = param 287 } 288 289 def wakeUpSourceExuIdx: Seq[Int] = { 290 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 291 } 292 293 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 294 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 295 } 296 297 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 298 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 299 } 300 301 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 302 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 303 } 304 305 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 306 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 307 } 308 309 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 310 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 311 } 312 313 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 314 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 315 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 316 case _ => Seq() 317 } 318 val vfBundle = schdType match { 319 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 320 case _ => Seq() 321 } 322 MixedVec(intBundle ++ vfBundle) 323 } 324 325 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 326 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 327 } 328 329 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 330 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 331 } 332 333 def genOGRespBundle(implicit p: Parameters) = { 334 implicit val issueBlockParams = this 335 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 336 } 337 338 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 339 implicit val issueBlockParams = this 340 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 341 } 342 343 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 344 implicit val issueBlockParams = this 345 MixedVec(exuBlockParams.map{ x => 346 new WbFuBusyTableReadBundle(x) 347 }) 348 } 349 350 def genWbConflictBundle()(implicit p: Parameters) = { 351 implicit val issueBlockParams = this 352 MixedVec(exuBlockParams.map { x => 353 new WbConflictBundle(x) 354 }) 355 } 356 357 def getIQName = { 358 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 359 } 360 361 def getEntryName = { 362 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 363 } 364} 365