1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15import xiangshan.backend.issue.EntryBundles.EntryDeqRespBundle 16 17case class IssueBlockParams( 18 // top down 19 private val exuParams: Seq[ExeUnitParams], 20 val numEntries : Int, 21 numEnq : Int, 22 numComp : Int, 23 numDeqOutside : Int = 0, 24 numWakeupFromOthers : Int = 0, 25 XLEN : Int = 64, 26 VLEN : Int = 128, 27 vaddrBits : Int = 39, 28 // calculate in scheduler 29 var idxInSchBlk : Int = 0, 30)( 31 implicit 32 val schdType: SchedulerType, 33) { 34 var backendParam: BackendParams = null 35 36 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 37 38 val allExuParams = exuParams 39 40 def updateIdx(idx: Int): Unit = { 41 this.idxInSchBlk = idx 42 } 43 44 def inMemSchd: Boolean = schdType == MemScheduler() 45 46 def inIntSchd: Boolean = schdType == IntScheduler() 47 48 def inVfSchd: Boolean = schdType == VfScheduler() 49 50 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 51 52 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 53 54 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 55 56 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 57 58 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 59 60 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 61 62 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 63 64 def needFeedBackSqIdx: Boolean = isVecMemIQ || isStAddrIQ 65 66 def needFeedBackLqIdx: Boolean = isVecMemIQ || isLdAddrIQ 67 68 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 69 70 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 71 72 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 73 74 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 75 76 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 77 78 def numV0Src: Int = exuBlockParams.map(_.numV0Src).max 79 80 def numVlSrc: Int = exuBlockParams.map(_.numVlSrc).max 81 82 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 83 84 def numSrc: Int = exuBlockParams.map(_.numSrc).max 85 86 def readIntRf: Boolean = numIntSrc > 0 87 88 def readFpRf: Boolean = numFpSrc > 0 89 90 def readVecRf: Boolean = numVecSrc > 0 91 92 def readVfRf: Boolean = numVfSrc > 0 93 94 def readV0Rf: Boolean = numV0Src > 0 95 96 def readVlRf: Boolean = numVlSrc > 0 97 98 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 99 100 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 101 102 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 103 104 def writeV0Rf: Boolean = exuBlockParams.map(_.writeV0Rf).reduce(_ || _) 105 106 def writeVlRf: Boolean = exuBlockParams.map(_.writeVlRf).reduce(_ || _) 107 108 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 109 110 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 111 112 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 113 114 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 115 116 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 117 118 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 119 120 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 121 122 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 123 124 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 125 126 def writeVConfig: Boolean = exuBlockParams.map(_.writeVConfig).reduce(_ || _) 127 128 def writeVType: Boolean = exuBlockParams.map(_.writeVType).reduce(_ || _) 129 130 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 131 132 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 133 134 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 135 136 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 137 138 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 139 140 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 141 142 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 143 144 def numDeq: Int = numDeqOutside + exuBlockParams.length 145 146 def numSimp: Int = numEntries - numEnq - numComp 147 148 def isAllComp: Boolean = numComp == (numEntries - numEnq) 149 150 def isAllSimp: Boolean = numComp == 0 151 152 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 153 154 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 155 156 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 157 158 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 159 160 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 161 162 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 163 164 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 165 166 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 167 168 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 169 170 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 171 172 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 173 174 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 175 176 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 177 178 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 179 180 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 181 182 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 183 184 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 185 186 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 187 188 def LdExuCnt = LduCnt + HyuCnt 189 190 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 191 192 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 193 194 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 195 196 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 197 198 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 199 200 def numWriteRegCache: Int = exuBlockParams.map(x => if (x.needWriteRegCache) 1 else 0).sum 201 202 def needWriteRegCache: Boolean = numWriteRegCache > 0 203 204 /** 205 * Get the regfile type that this issue queue need to read 206 */ 207 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 208 209 /** 210 * Get the regfile type that this issue queue need to read 211 */ 212 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 213 214 /** 215 * Get the max width of psrc 216 */ 217 def rdPregIdxWidth = { 218 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 219 } 220 221 /** 222 * Get the max width of pdest 223 */ 224 def wbPregIdxWidth = { 225 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 226 } 227 228 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 229 230 /** Get exu source wake up 231 * @todo replace with 232 * exuBlockParams 233 * .flatMap(_.iqWakeUpSinkPairs) 234 * .map(_.source) 235 * .distinctBy(_.name) 236 * when xiangshan is updated to 2.13.11 237 */ 238 def wakeUpInExuSources: Seq[WakeUpSource] = { 239 SeqUtils.distinctBy( 240 exuBlockParams 241 .flatMap(_.iqWakeUpSinkPairs) 242 .map(_.source) 243 )(_.name) 244 } 245 246 def wakeUpOutExuSources: Seq[WakeUpSource] = { 247 SeqUtils.distinctBy( 248 exuBlockParams 249 .flatMap(_.iqWakeUpSourcePairs) 250 .map(_.source) 251 )(_.name) 252 } 253 254 def wakeUpToExuSinks = exuBlockParams 255 .flatMap(_.iqWakeUpSourcePairs) 256 .map(_.sink).distinct 257 258 def numWakeupToIQ: Int = wakeUpInExuSources.size 259 260 def numWakeupFromIQ: Int = wakeUpInExuSources.size 261 262 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 263 264 def numWakeupFromWB = { 265 val pregSet = this.pregReadSet 266 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 267 } 268 269 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 270 271 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readIntRf).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 272 273 def needWakeupFromFpWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readFpRf).groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 274 275 def needWakeupFromVfWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVecRf).groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 276 277 def needWakeupFromV0WBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readV0Rf).groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 278 279 def needWakeupFromVlWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVlRf).groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 280 281 def hasWakeupFromMem: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isMemExeUnit).fold(false)(_ | _) 282 283 def hasWakeupFromVf: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isVfExeUnit).fold(false)(_ | _) 284 285 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 286 287 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 288 289 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 290 291 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 292 293 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 294 295 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 296 297 // set load imm to 32-bit for fused_lui_load 298 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 299 300 def needImm: Boolean = deqImmTypes.nonEmpty 301 302 // cfgs(exuIdx)(set of exu's wb) 303 304 /** 305 * Get [[PregWB]] of this IssueBlock 306 * @return set of [[PregWB]] of [[ExeUnit]] 307 */ 308 def getWbCfgs: Seq[Set[PregWB]] = { 309 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 310 } 311 312 def canAccept(fuType: UInt): Bool = { 313 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 314 } 315 316 def bindBackendParam(param: BackendParams): Unit = { 317 backendParam = param 318 } 319 320 def wakeUpSourceExuIdx: Seq[Int] = { 321 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 322 } 323 324 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 325 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 326 } 327 328 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 329 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 330 } 331 332 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 333 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 334 } 335 336 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 337 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 338 } 339 340 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 341 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 342 } 343 344 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 345 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 346 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 347 case _ => Seq() 348 } 349 val fpBundle = schdType match { 350 case FpScheduler() | MemScheduler() => needWakeupFromFpWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 351 case _ => Seq() 352 } 353 val vfBundle = schdType match { 354 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 355 case _ => Seq() 356 } 357 val v0Bundle = schdType match { 358 case VfScheduler() | MemScheduler() => needWakeupFromV0WBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 359 case _ => Seq() 360 } 361 val vlBundle = schdType match { 362 case VfScheduler() | MemScheduler() => needWakeupFromVlWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 363 case _ => Seq() 364 } 365 MixedVec(intBundle ++ fpBundle ++ vfBundle ++ v0Bundle ++ vlBundle) 366 } 367 368 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 369 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 370 } 371 372 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 373 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 374 } 375 376 def genOGRespBundle(implicit p: Parameters) = { 377 implicit val issueBlockParams = this 378 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 379 } 380 381 def genOG2RespBundle(implicit p: Parameters) = { 382 implicit val issueBlockParams = this 383 MixedVec(exuBlockParams.map(_ => new Valid(new EntryDeqRespBundle))) 384 } 385 386 def genWbFuBusyTableWriteBundle(implicit p: Parameters) = { 387 implicit val issueBlockParams = this 388 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 389 } 390 391 def genWbFuBusyTableReadBundle(implicit p: Parameters) = { 392 implicit val issueBlockParams = this 393 MixedVec(exuBlockParams.map{ x => 394 new WbFuBusyTableReadBundle(x) 395 }) 396 } 397 398 def genWbConflictBundle()(implicit p: Parameters) = { 399 implicit val issueBlockParams = this 400 MixedVec(exuBlockParams.map { x => 401 new WbConflictBundle(x) 402 }) 403 } 404 405 def getIQName = { 406 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 407 } 408 409 def getEntryName = { 410 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 411 } 412} 413