1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15import xiangshan.backend.issue.EntryBundles.EntryDeqRespBundle 16 17case class IssueBlockParams( 18 // top down 19 private val exuParams: Seq[ExeUnitParams], 20 val numEntries : Int, 21 numEnq : Int, 22 numComp : Int, 23 numDeqOutside : Int = 0, 24 numWakeupFromOthers : Int = 0, 25 XLEN : Int = 64, 26 VLEN : Int = 128, 27 vaddrBits : Int = 39, 28 // calculate in scheduler 29 var idxInSchBlk : Int = 0, 30)( 31 implicit 32 val schdType: SchedulerType, 33) { 34 var backendParam: BackendParams = null 35 36 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 37 38 val allExuParams = exuParams 39 40 def updateIdx(idx: Int): Unit = { 41 this.idxInSchBlk = idx 42 } 43 44 def inMemSchd: Boolean = schdType == MemScheduler() 45 46 def inIntSchd: Boolean = schdType == IntScheduler() 47 48 def inVfSchd: Boolean = schdType == VfScheduler() 49 50 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 51 52 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 53 54 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 55 56 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 57 58 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 59 60 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 61 62 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 63 64 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 65 66 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 67 68 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 69 70 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 71 72 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 73 74 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 75 76 def numSrc: Int = exuBlockParams.map(_.numSrc).max 77 78 def readIntRf: Boolean = numIntSrc > 0 79 80 def readFpRf: Boolean = numFpSrc > 0 81 82 def readVecRf: Boolean = numVecSrc > 0 83 84 def readVfRf: Boolean = numVfSrc > 0 85 86 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 87 88 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 89 90 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 91 92 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 93 94 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 95 96 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 97 98 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 99 100 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 101 102 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 103 104 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 105 106 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 107 108 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 109 110 def writeVConfig: Boolean = exuBlockParams.map(_.writeVConfig).reduce(_ || _) 111 112 def writeVType: Boolean = exuBlockParams.map(_.writeVType).reduce(_ || _) 113 114 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 115 116 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 117 118 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 119 120 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 121 122 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 123 124 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 125 126 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 127 128 def numDeq: Int = numDeqOutside + exuBlockParams.length 129 130 def numSimp: Int = numEntries - numEnq - numComp 131 132 def isAllComp: Boolean = numComp == (numEntries - numEnq) 133 134 def isAllSimp: Boolean = numComp == 0 135 136 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 137 138 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 139 140 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 141 142 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 143 144 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 145 146 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 147 148 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 149 150 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 151 152 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 153 154 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 155 156 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 157 158 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 159 160 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 161 162 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 163 164 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 165 166 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 167 168 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 169 170 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 171 172 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 173 174 def LdExuCnt = LduCnt + HyuCnt 175 176 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 177 178 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 179 180 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 181 182 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 183 184 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 185 186 /** 187 * Get the regfile type that this issue queue need to read 188 */ 189 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 190 191 /** 192 * Get the regfile type that this issue queue need to read 193 */ 194 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 195 196 /** 197 * Get the max width of psrc 198 */ 199 def rdPregIdxWidth = { 200 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 201 } 202 203 /** 204 * Get the max width of pdest 205 */ 206 def wbPregIdxWidth = { 207 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 208 } 209 210 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 211 212 /** Get exu source wake up 213 * @todo replace with 214 * exuBlockParams 215 * .flatMap(_.iqWakeUpSinkPairs) 216 * .map(_.source) 217 * .distinctBy(_.name) 218 * when xiangshan is updated to 2.13.11 219 */ 220 def wakeUpInExuSources: Seq[WakeUpSource] = { 221 SeqUtils.distinctBy( 222 exuBlockParams 223 .flatMap(_.iqWakeUpSinkPairs) 224 .map(_.source) 225 )(_.name) 226 } 227 228 def wakeUpOutExuSources: Seq[WakeUpSource] = { 229 SeqUtils.distinctBy( 230 exuBlockParams 231 .flatMap(_.iqWakeUpSourcePairs) 232 .map(_.source) 233 )(_.name) 234 } 235 236 def wakeUpToExuSinks = exuBlockParams 237 .flatMap(_.iqWakeUpSourcePairs) 238 .map(_.sink).distinct 239 240 def numWakeupToIQ: Int = wakeUpInExuSources.size 241 242 def numWakeupFromIQ: Int = wakeUpInExuSources.size 243 244 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 245 246 def numWakeupFromWB = { 247 val pregSet = this.pregReadSet 248 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 249 } 250 251 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 252 253 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 254 255 def needWakeupFromVfWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 256 257 def hasWakeupFromMem: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isMemExeUnit).fold(false)(_ | _) 258 259 def hasWakeupFromVf: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isVfExeUnit).fold(false)(_ | _) 260 261 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 262 263 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 264 265 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 266 267 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 268 269 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 270 271 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 272 273 // set load imm to 32-bit for fused_lui_load 274 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 275 276 def needImm: Boolean = deqImmTypes.nonEmpty 277 278 // cfgs(exuIdx)(set of exu's wb) 279 280 /** 281 * Get [[PregWB]] of this IssueBlock 282 * @return set of [[PregWB]] of [[ExeUnit]] 283 */ 284 def getWbCfgs: Seq[Set[PregWB]] = { 285 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 286 } 287 288 def canAccept(fuType: UInt): Bool = { 289 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 290 } 291 292 def bindBackendParam(param: BackendParams): Unit = { 293 backendParam = param 294 } 295 296 def wakeUpSourceExuIdx: Seq[Int] = { 297 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 298 } 299 300 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 301 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 302 } 303 304 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 305 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 306 } 307 308 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 309 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 310 } 311 312 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 313 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 314 } 315 316 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 317 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 318 } 319 320 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 321 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 322 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 323 case _ => Seq() 324 } 325 val vfBundle = schdType match { 326 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 327 case _ => Seq() 328 } 329 MixedVec(intBundle ++ vfBundle) 330 } 331 332 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 333 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 334 } 335 336 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 337 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 338 } 339 340 def genOGRespBundle(implicit p: Parameters) = { 341 implicit val issueBlockParams = this 342 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 343 } 344 345 def genOG2RespBundle(implicit p: Parameters) = { 346 implicit val issueBlockParams = this 347 MixedVec(exuBlockParams.map(_ => new Valid(new EntryDeqRespBundle))) 348 } 349 350 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 351 implicit val issueBlockParams = this 352 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 353 } 354 355 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 356 implicit val issueBlockParams = this 357 MixedVec(exuBlockParams.map{ x => 358 new WbFuBusyTableReadBundle(x) 359 }) 360 } 361 362 def genWbConflictBundle()(implicit p: Parameters) = { 363 implicit val issueBlockParams = this 364 MixedVec(exuBlockParams.map { x => 365 new WbConflictBundle(x) 366 }) 367 } 368 369 def getIQName = { 370 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 371 } 372 373 def getEntryName = { 374 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 375 } 376} 377