1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package top 19 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import system._ 26import org.chipsalliance.cde.config._ 27import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, MaxHartIdBits, XLen} 28import xiangshan.frontend.icache.ICacheParameters 29import freechips.rocketchip.devices.debug._ 30import openLLC.OpenLLCParam 31import freechips.rocketchip.diplomacy._ 32import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 33import xiangshan.cache.DCacheParameters 34import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 35import device.EnableJtag 36import huancun._ 37import coupledL2._ 38import coupledL2.prefetch._ 39 40class BaseConfig(n: Int) extends Config((site, here, up) => { 41 case XLen => 64 42 case DebugOptionsKey => DebugOptions() 43 case SoCParamsKey => SoCParameters() 44 case CVMParamskey => CVMParameters() 45 case PMParameKey => PMParameters() 46 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 47 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 48 case DebugModuleKey => Some(DebugModuleParams( 49 nAbstractDataWords = (if (site(XLen) == 32) 1 else if (site(XLen) == 64) 2 else 4), 50 maxSupportedSBAccess = site(XLen), 51 hasBusMaster = true, 52 baseAddress = BigInt(0x38020000), 53 nScratch = 2, 54 crossingHasSafeReset = false, 55 hasHartResets = true 56 )) 57 case JtagDTMKey => JtagDTMKey 58 case MaxHartIdBits => log2Up(n) max 6 59 case EnableJtag => true.B 60}) 61 62// Synthesizable minimal XiangShan 63// * It is still an out-of-order, super-scalaer arch 64// * L1 cache included 65// * L2 cache NOT included 66// * L3 cache included 67class MinimalConfig(n: Int = 1) extends Config( 68 new BaseConfig(n).alter((site, here, up) => { 69 case XSTileKey => up(XSTileKey).map( 70 p => p.copy( 71 DecodeWidth = 6, 72 RenameWidth = 6, 73 RobCommitWidth = 8, 74 // FetchWidth = 4, // NOTE: make sure that FTQ SRAM width is not a prime number bigger than 256. 75 VirtualLoadQueueSize = 24, 76 LoadQueueRARSize = 24, 77 LoadQueueRAWSize = 12, 78 LoadQueueReplaySize = 24, 79 LoadUncacheBufferSize = 8, 80 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 81 RollbackGroupSize = 8, 82 StoreQueueSize = 20, 83 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 84 StoreQueueForwardWithMask = true, 85 // ============ VLSU ============ 86 VlMergeBufferSize = 16, 87 VsMergeBufferSize = 8, 88 UopWritebackWidth = 2, 89 // ============================== 90 RobSize = 48, 91 RabSize = 96, 92 FtqSize = 8, 93 IBufSize = 24, 94 IBufNBank = 6, 95 StoreBufferSize = 4, 96 StoreBufferThreshold = 3, 97 IssueQueueSize = 10, 98 IssueQueueCompEntrySize = 4, 99 intPreg = IntPregParams( 100 numEntries = 64, 101 numRead = None, 102 numWrite = None, 103 ), 104 vfPreg = VfPregParams( 105 numEntries = 160, 106 numRead = None, 107 numWrite = None, 108 ), 109 icacheParameters = ICacheParameters( 110 nSets = 64, // 16KB ICache 111 tagECC = Some("parity"), 112 dataECC = Some("parity"), 113 replacer = Some("setplru"), 114 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)), 115 ), 116 dcacheParametersOpt = Some(DCacheParameters( 117 nSets = 64, // 32KB DCache 118 nWays = 8, 119 tagECC = Some("secded"), 120 dataECC = Some("secded"), 121 replacer = Some("setplru"), 122 nMissEntries = 4, 123 nProbeEntries = 4, 124 nReleaseEntries = 8, 125 nMaxPrefetchEntry = 2, 126 enableTagEcc = true, 127 enableDataEcc = true, 128 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 129 )), 130 // ============ BPU =============== 131 EnableLoop = false, 132 EnableGHistDiff = false, 133 FtbSize = 256, 134 FtbWays = 2, 135 RasSize = 8, 136 RasSpecSize = 16, 137 TageTableInfos = 138 Seq((512, 4, 6), 139 (512, 9, 6), 140 (1024, 19, 6)), 141 SCNRows = 128, 142 SCNTables = 2, 143 SCHistLens = Seq(0, 5), 144 ITTageTableInfos = 145 Seq((256, 4, 7), 146 (256, 8, 7), 147 (512, 16, 7)), 148 // ================================ 149 itlbParameters = TLBParameters( 150 name = "itlb", 151 fetchi = true, 152 useDmode = false, 153 NWays = 4, 154 ), 155 ldtlbParameters = TLBParameters( 156 name = "ldtlb", 157 NWays = 4, 158 partialStaticPMP = true, 159 outsideRecvFlush = true, 160 outReplace = false, 161 lgMaxSize = 4 162 ), 163 sttlbParameters = TLBParameters( 164 name = "sttlb", 165 NWays = 4, 166 partialStaticPMP = true, 167 outsideRecvFlush = true, 168 outReplace = false, 169 lgMaxSize = 4 170 ), 171 hytlbParameters = TLBParameters( 172 name = "hytlb", 173 NWays = 4, 174 partialStaticPMP = true, 175 outsideRecvFlush = true, 176 outReplace = false, 177 lgMaxSize = 4 178 ), 179 pftlbParameters = TLBParameters( 180 name = "pftlb", 181 NWays = 4, 182 partialStaticPMP = true, 183 outsideRecvFlush = true, 184 outReplace = false, 185 lgMaxSize = 4 186 ), 187 btlbParameters = TLBParameters( 188 name = "btlb", 189 NWays = 4, 190 ), 191 l2tlbParameters = L2TLBParameters( 192 l3Size = 4, 193 l2Size = 4, 194 l1nSets = 4, 195 l1nWays = 4, 196 l1ReservedBits = 1, 197 l0nSets = 4, 198 l0nWays = 8, 199 l0ReservedBits = 0, 200 spSize = 4, 201 ), 202 L2CacheParamsOpt = Some(L2Param( 203 name = "L2", 204 ways = 8, 205 sets = 128, 206 echoField = Seq(huancun.DirtyField()), 207 prefetch = Nil, 208 clientCaches = Seq(L1Param( 209 "dcache", 210 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 211 )), 212 )), 213 L2NBanks = 2, 214 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 215 ) 216 ) 217 case SoCParamsKey => 218 val tiles = site(XSTileKey) 219 up(SoCParamsKey).copy( 220 L3CacheParamsOpt = Option.when(!up(EnableCHI))(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 221 sets = 1024, 222 inclusive = false, 223 clientCaches = tiles.map{ core => 224 val clientDirBytes = tiles.map{ t => 225 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 226 }.sum 227 val l2params = core.L2CacheParamsOpt.get.toCacheParams 228 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 229 }, 230 simulation = !site(DebugOptionsKey).FPGAPlatform, 231 prefetch = None 232 )), 233 OpenLLCParamsOpt = Option.when(up(EnableCHI))(OpenLLCParam( 234 name = "LLC", 235 ways = 8, 236 sets = 2048, 237 banks = 4, 238 clientCaches = Seq(L2Param()) 239 )), 240 L3NBanks = 1 241 ) 242 }) 243) 244 245// Non-synthesizable MinimalConfig, for fast simulation only 246class MinimalSimConfig(n: Int = 1) extends Config( 247 new MinimalConfig(n).alter((site, here, up) => { 248 case XSTileKey => up(XSTileKey).map(_.copy( 249 dcacheParametersOpt = None, 250 softPTW = true 251 )) 252 case SoCParamsKey => up(SoCParamsKey).copy( 253 L3CacheParamsOpt = None, 254 OpenLLCParamsOpt = None 255 ) 256 }) 257) 258 259case class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 260 case XSTileKey => 261 val sets = n * 1024 / ways / 64 262 up(XSTileKey).map(_.copy( 263 dcacheParametersOpt = Some(DCacheParameters( 264 nSets = sets, 265 nWays = ways, 266 tagECC = Some("secded"), 267 dataECC = Some("secded"), 268 replacer = Some("setplru"), 269 nMissEntries = 16, 270 nProbeEntries = 8, 271 nReleaseEntries = 18, 272 nMaxPrefetchEntry = 6, 273 enableTagEcc = true, 274 enableDataEcc = true, 275 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 276 )) 277 )) 278}) 279 280case class L2CacheConfig 281( 282 size: String, 283 ways: Int = 8, 284 inclusive: Boolean = true, 285 banks: Int = 1, 286 tp: Boolean = true 287) extends Config((site, here, up) => { 288 case XSTileKey => 289 require(inclusive, "L2 must be inclusive") 290 val nKB = size.toUpperCase() match { 291 case s"${k}KB" => k.trim().toInt 292 case s"${m}MB" => (m.trim().toDouble * 1024).toInt 293 } 294 val upParams = up(XSTileKey) 295 val l2sets = nKB * 1024 / banks / ways / 64 296 upParams.map(p => p.copy( 297 L2CacheParamsOpt = Some(L2Param( 298 name = "L2", 299 ways = ways, 300 sets = l2sets, 301 clientCaches = Seq(L1Param( 302 "dcache", 303 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 304 ways = p.dcacheParametersOpt.get.nWays + 2, 305 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 306 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 307 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 308 )), 309 reqField = Seq(utility.ReqSourceField()), 310 echoField = Seq(huancun.DirtyField()), 311 tagECC = Some("secded"), 312 dataECC = Some("secded"), 313 enableTagECC = true, 314 enableDataECC = true, 315 dataCheck = Some("oddparity"), 316 enablePoison = true, 317 prefetch = Seq(BOPParameters()) ++ 318 (if (tp) Seq(TPParameters()) else Nil) ++ 319 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 320 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 321 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 322 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 323 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform, 324 hasMbist = p.hasMbist, 325 hasSramCtl = p.hasSramCtl, 326 )), 327 L2NBanks = banks 328 )) 329}) 330 331case class L3CacheConfig(size: String, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 332 case SoCParamsKey => 333 val nKB = size.toUpperCase() match { 334 case s"${k}KB" => k.trim().toInt 335 case s"${m}MB" => (m.trim().toDouble * 1024).toInt 336 } 337 val sets = nKB * 1024 / banks / ways / 64 338 val tiles = site(XSTileKey) 339 val clientDirBytes = tiles.map{ t => 340 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 341 }.sum 342 up(SoCParamsKey).copy( 343 L3NBanks = banks, 344 L3CacheParamsOpt = Option.when(!up(EnableCHI))(HCCacheParameters( 345 name = "L3", 346 level = 3, 347 ways = ways, 348 sets = sets, 349 inclusive = inclusive, 350 clientCaches = tiles.map{ core => 351 val l2params = core.L2CacheParamsOpt.get.toCacheParams 352 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 353 }, 354 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 355 ctrl = Some(CacheCtrl( 356 address = 0x39000000, 357 numCores = tiles.size 358 )), 359 reqField = Seq(utility.ReqSourceField()), 360 sramClkDivBy2 = true, 361 sramDepthDiv = 4, 362 tagECC = Some("secded"), 363 dataECC = Some("secded"), 364 simulation = !site(DebugOptionsKey).FPGAPlatform, 365 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 366 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 367 )), 368 OpenLLCParamsOpt = Option.when(up(EnableCHI))(OpenLLCParam( 369 name = "LLC", 370 ways = ways, 371 sets = sets, 372 banks = banks, 373 fullAddressBits = 48, 374 clientCaches = tiles.map { core => 375 val l2params = core.L2CacheParamsOpt.get 376 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 377 }, 378 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 379 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 380 )) 381 ) 382}) 383 384class WithL3DebugConfig extends Config( 385 L3CacheConfig("256KB", inclusive = false) ++ L2CacheConfig("64KB") 386) 387 388class MinimalL3DebugConfig(n: Int = 1) extends Config( 389 new WithL3DebugConfig ++ new MinimalConfig(n) 390) 391 392class DefaultL3DebugConfig(n: Int = 1) extends Config( 393 new WithL3DebugConfig ++ new BaseConfig(n) 394) 395 396class WithFuzzer extends Config((site, here, up) => { 397 case DebugOptionsKey => up(DebugOptionsKey).copy( 398 EnablePerfDebug = false, 399 ) 400 case SoCParamsKey => up(SoCParamsKey).copy( 401 L3CacheParamsOpt = up(SoCParamsKey).L3CacheParamsOpt.map(_.copy( 402 enablePerf = false, 403 )), 404 OpenLLCParamsOpt = up(SoCParamsKey).OpenLLCParamsOpt.map(_.copy( 405 enablePerf = false, 406 )), 407 ) 408 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 409 p.copy( 410 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 411 enablePerf = false, 412 )), 413 ) 414 } 415}) 416 417class CVMCompile extends Config((site, here, up) => { 418 case CVMParamskey => up(CVMParamskey).copy( 419 KeyIDBits = 5, 420 HasMEMencryption = true, 421 HasDelayNoencryption = false 422 ) 423 case XSTileKey => up(XSTileKey).map(_.copy( 424 HasBitmapCheck = true, 425 HasBitmapCheckDefault = false)) 426}) 427 428class CVMTestCompile extends Config((site, here, up) => { 429 case CVMParamskey => up(CVMParamskey).copy( 430 KeyIDBits = 5, 431 HasMEMencryption = true, 432 HasDelayNoencryption = true 433 ) 434 case XSTileKey => up(XSTileKey).map(_.copy( 435 HasBitmapCheck =true, 436 HasBitmapCheckDefault = true)) 437}) 438 439class MinimalAliasDebugConfig(n: Int = 1) extends Config( 440 L3CacheConfig("512KB", inclusive = false) 441 ++ L2CacheConfig("256KB", inclusive = true) 442 ++ WithNKBL1D(128) 443 ++ new MinimalConfig(n) 444) 445 446class MediumConfig(n: Int = 1) extends Config( 447 L3CacheConfig("4MB", inclusive = false, banks = 4) 448 ++ L2CacheConfig("512KB", inclusive = true) 449 ++ WithNKBL1D(128) 450 ++ new BaseConfig(n) 451) 452 453class FuzzConfig(dummy: Int = 0) extends Config( 454 new WithFuzzer 455 ++ new DefaultConfig(1) 456) 457 458class DefaultConfig(n: Int = 1) extends Config( 459 L3CacheConfig("16MB", inclusive = false, banks = 4, ways = 16) 460 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 461 ++ WithNKBL1D(64, ways = 4) 462 ++ new BaseConfig(n) 463) 464 465class CVMConfig(n: Int = 1) extends Config( 466 new CVMCompile 467 ++ new DefaultConfig(n) 468) 469 470class CVMTestConfig(n: Int = 1) extends Config( 471 new CVMTestCompile 472 ++ new DefaultConfig(n) 473) 474 475class WithCHI extends Config((_, _, _) => { 476 case EnableCHI => true 477}) 478 479class KunminghuV2Config(n: Int = 1) extends Config( 480 L2CacheConfig("1MB", inclusive = true, banks = 4, tp = false) 481 ++ new DefaultConfig(n) 482 ++ new WithCHI 483) 484 485class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 486 L2CacheConfig("128KB", inclusive = true, banks = 1, tp = false) 487 ++ WithNKBL1D(32, ways = 4) 488 ++ new MinimalConfig(n) 489 ++ new WithCHI 490) 491 492class XSNoCTopConfig(n: Int = 1) extends Config( 493 (new KunminghuV2Config(n)).alter((site, here, up) => { 494 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 495 }) 496) 497 498class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 499 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 500 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 501 }) 502) 503 504class XSNoCDiffTopConfig(n: Int = 1) extends Config( 505 (new XSNoCTopConfig(n)).alter((site, here, up) => { 506 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCDiffTop = true) 507 }) 508) 509 510class XSNoCDiffTopMinimalConfig(n: Int = 1) extends Config( 511 (new XSNoCTopConfig(n)).alter((site, here, up) => { 512 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCDiffTop = true) 513 }) 514) 515 516class FpgaDefaultConfig(n: Int = 1) extends Config( 517 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 518 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 519 ++ WithNKBL1D(64, ways = 4) 520 ++ new BaseConfig(n)).alter((site, here, up) => { 521 case DebugOptionsKey => up(DebugOptionsKey).copy( 522 AlwaysBasicDiff = false, 523 AlwaysBasicDB = false 524 ) 525 case SoCParamsKey => up(SoCParamsKey).copy( 526 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 527 sramClkDivBy2 = false, 528 )), 529 ) 530 }) 531) 532 533class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 534 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 535 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 536 ++ WithNKBL1D(64, ways = 4) 537 ++ new BaseConfig(n)).alter((site, here, up) => { 538 case DebugOptionsKey => up(DebugOptionsKey).copy( 539 AlwaysBasicDiff = true, 540 AlwaysBasicDB = false 541 ) 542 case SoCParamsKey => up(SoCParamsKey).copy( 543 UseXSTileDiffTop = true, 544 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 545 sramClkDivBy2 = false, 546 )), 547 ) 548 }) 549) 550 551class FpgaDiffMinimalConfig(n: Int = 1) extends Config( 552 (new MinimalConfig(n)).alter((site, here, up) => { 553 case DebugOptionsKey => up(DebugOptionsKey).copy( 554 AlwaysBasicDiff = true, 555 AlwaysBasicDB = false 556 ) 557 case SoCParamsKey => up(SoCParamsKey).copy( 558 UseXSTileDiffTop = true, 559 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 560 sramClkDivBy2 = false, 561 )), 562 ) 563 }) 564) 565