xref: /XiangShan/src/main/scala/system/SoC.scala (revision aad61829667df24ef0dc5e649eafb6bf2e747c98) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44  EnableILA: Boolean = false,
45  PAddrBits: Int = 48,
46  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
47  PMAConfigs: Seq[PMAConfigEntry] = Seq(
48    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
49    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
50    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
51    PMAConfigEntry(0x3A000000L, a = 1),
52    PMAConfigEntry(0x39002000L, a = 1, w = true, r = true),
53    PMAConfigEntry(0x39000000L, a = 1, w = true, r = true),
54    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
55    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
56    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
57    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
58    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
59    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
60    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
61    PMAConfigEntry(0)
62  ),
63  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
64  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
65  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
66  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
67  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
68  extIntrs: Int = 64,
69  L3NBanks: Int = 4,
70  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
71    name = "L3",
72    level = 3,
73    ways = 8,
74    sets = 2048 // 1MB per bank
75  )),
76  OpenLLCParamsOpt: Option[OpenLLCParam] = None,
77  XSTopPrefix: Option[String] = None,
78  NodeIDWidthList: Map[String, Int] = Map(
79    "B" -> 7,
80    "C" -> 9,
81    "E.b" -> 11
82  ),
83  NumHart: Int = 64,
84  NumIRFiles: Int = 7,
85  NumIRSrc: Int = 256,
86  UseXSNoCTop: Boolean = false,
87  UseXSNoCDiffTop: Boolean = false,
88  IMSICUseTL: Boolean = false,
89  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
90  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
91){
92  require(
93    L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,
94    "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined"
95  )
96  // L3 configurations
97  val L3InnerBusWidth = 256
98  val L3BlockSize = 64
99  // on chip network configurations
100  val L3OuterBusWidth = 256
101  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
102}
103
104trait HasSoCParameter {
105  implicit val p: Parameters
106
107  val soc = p(SoCParamsKey)
108  val debugOpts = p(DebugOptionsKey)
109  val tiles = p(XSTileKey)
110  val enableCHI = p(EnableCHI)
111  val issue = p(CHIIssue)
112
113  val NumCores = tiles.size
114  val EnableILA = soc.EnableILA
115
116  // Parameters for trace extension
117  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
118  val TraceCauseWidth             = tiles.head.XLEN
119  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
120  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
121  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
122  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
123  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
124  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
125
126  // L3 configurations
127  val L3InnerBusWidth = soc.L3InnerBusWidth
128  val L3BlockSize = soc.L3BlockSize
129  val L3NBanks = soc.L3NBanks
130
131  // on chip network configurations
132  val L3OuterBusWidth = soc.L3OuterBusWidth
133
134  val NrExtIntr = soc.extIntrs
135
136  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
137
138  val NumIRSrc = soc.NumIRSrc
139
140  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
141    soc.EnableCHIAsyncBridge else None
142  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
143}
144
145trait HasPeripheralRanges {
146  implicit val p: Parameters
147
148  private def soc = p(SoCParamsKey)
149  private def dm = p(DebugModuleKey)
150  private def pmParams = p(PMParameKey)
151
152  private def mmpma = pmParams.mmpma
153
154  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
155    "CLINT" -> soc.CLINTRange,
156    "BEU"   -> soc.BEURange,
157    "PLIC"  -> soc.PLICRange,
158    "PLL"   -> soc.PLLRange,
159    "UART"  -> soc.UARTLiteRange,
160    "DEBUG" -> dm.get.address,
161    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
162  ) ++ (
163    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
164      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
165    else
166      Map()
167  )
168
169  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
170    acc.flatMap(_.subtract(x))
171  }
172}
173
174class ILABundle extends Bundle {}
175
176
177abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
178  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
179  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
180  val l3_xbar = Option.when(!enableCHI)(TLXbar())
181  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
182
183  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
184}
185
186// We adapt the following three traits from rocket-chip.
187// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
188trait HaveSlaveAXI4Port {
189  this: BaseSoC =>
190
191  val idBits = 14
192
193  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
194    Seq(AXI4MasterParameters(
195      name = "dma",
196      id = IdRange(0, 1 << idBits)
197    ))
198  )))
199
200  if (l3_xbar.isDefined) {
201    val errorDevice = LazyModule(new TLError(
202      params = DevNullParams(
203        address = Seq(AddressSet(0x0, 0x7fffffffL)),
204        maxAtomic = 8,
205        maxTransfer = 64),
206      beatBytes = L3InnerBusWidth / 8
207    ))
208    errorDevice.node :=
209      l3_xbar.get :=
210      TLFIFOFixer() :=
211      TLWidthWidget(32) :=
212      AXI4ToTL() :=
213      AXI4UserYanker(Some(1)) :=
214      AXI4Fragmenter() :=
215      AXI4Buffer() :=
216      AXI4Buffer() :=
217      AXI4IdIndexer(1) :=
218      l3FrontendAXI4Node
219  }
220
221  val dma = InModuleBody {
222    l3FrontendAXI4Node.makeIOs()
223  }
224}
225
226trait HaveAXI4MemPort {
227  this: BaseSoC =>
228  val device = new MemoryDevice
229  // 48-bit physical address
230  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
231  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
232    AXI4SlavePortParameters(
233      slaves = Seq(
234        AXI4SlaveParameters(
235          address = memRange,
236          regionType = RegionType.UNCACHED,
237          executable = true,
238          supportsRead = TransferSizes(1, L3BlockSize),
239          supportsWrite = TransferSizes(1, L3BlockSize),
240          interleavedId = Some(0),
241          resources = device.reg("mem")
242        )
243      ),
244      beatBytes = L3OuterBusWidth / 8,
245      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
246    )
247  ))
248
249  val mem_xbar = TLXbar()
250  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
251  val axi4mem_node = AXI4IdentityNode()
252
253  if (enableCHI) {
254    axi4mem_node :=
255      soc_xbar.get
256  } else {
257    mem_xbar :=*
258      TLBuffer.chainNode(2) :=
259      TLCacheCork() :=
260      l3_mem_pmu :=
261      TLClientsMerger() :=
262      TLXbar() :=*
263      bankedNode.get
264
265    mem_xbar :=
266      TLWidthWidget(8) :=
267      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
268      peripheralXbar.get
269
270    axi4mem_node :=
271      TLToAXI4() :=
272      TLSourceShrinker(64) :=
273      TLWidthWidget(L3OuterBusWidth / 8) :=
274      TLBuffer.chainNode(2) :=
275      mem_xbar
276  }
277
278  memAXI4SlaveNode :=
279    AXI4Buffer() :=
280    AXI4Buffer() :=
281    AXI4Buffer() :=
282    AXI4IdIndexer(idBits = 14) :=
283    AXI4UserYanker() :=
284    AXI4Deinterleaver(L3BlockSize) :=
285    axi4mem_node
286
287  val memory = InModuleBody {
288    memAXI4SlaveNode.makeIOs()
289  }
290}
291
292trait HaveAXI4PeripheralPort { this: BaseSoC =>
293  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
294  val uartParams = AXI4SlaveParameters(
295    address = Seq(soc.UARTLiteRange),
296    regionType = RegionType.UNCACHED,
297    supportsRead = TransferSizes(1, 32),
298    supportsWrite = TransferSizes(1, 32),
299    resources = uartDevice.reg
300  )
301  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
302    Seq(AXI4SlaveParameters(
303      address = peripheralRange,
304      regionType = RegionType.UNCACHED,
305      supportsRead = TransferSizes(1, 32),
306      supportsWrite = TransferSizes(1, 32),
307      interleavedId = Some(0)
308    ), uartParams),
309    beatBytes = 8
310  )))
311
312  val axi4peripheral_node = AXI4IdentityNode()
313  val error_xbar = Option.when(enableCHI)(TLXbar())
314
315  peripheralNode :=
316    AXI4UserYanker() :=
317    AXI4IdIndexer(idBits = 2) :=
318    AXI4Buffer() :=
319    AXI4Buffer() :=
320    AXI4Buffer() :=
321    AXI4Buffer() :=
322    AXI4UserYanker() :=
323    // AXI4Deinterleaver(8) :=
324    axi4peripheral_node
325
326  if (enableCHI) {
327    val error = LazyModule(new TLError(
328      params = DevNullParams(
329        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
330        maxAtomic = 8,
331        maxTransfer = 64),
332      beatBytes = 8
333    ))
334    error.node := error_xbar.get
335    axi4peripheral_node :=
336      AXI4Deinterleaver(8) :=
337      TLToAXI4() :=
338      error_xbar.get :=
339      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
340      TLFIFOFixer() :=
341      TLWidthWidget(L3OuterBusWidth / 8) :=
342      AXI4ToTL() :=
343      AXI4UserYanker() :=
344      soc_xbar.get
345  } else {
346    axi4peripheral_node :=
347      AXI4Deinterleaver(8) :=
348      TLToAXI4() :=
349      TLBuffer.chainNode(3) :=
350      peripheralXbar.get
351  }
352
353  val peripheral = InModuleBody {
354    peripheralNode.makeIOs()
355  }
356
357}
358
359class MemMisc()(implicit p: Parameters) extends BaseSoC
360  with HaveAXI4MemPort
361  with PMAConst
362  with HaveAXI4PeripheralPort
363{
364
365  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
366  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
367
368  val l3_in = TLTempNode()
369  val l3_out = TLTempNode()
370
371  val device_xbar = Option.when(enableCHI)(TLXbar())
372  device_xbar.foreach(_ := error_xbar.get)
373
374  if (l3_banked_xbar.isDefined) {
375    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
376    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
377  }
378  bankedNode match {
379    case Some(bankBinder) =>
380      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
381    case None =>
382  }
383
384  if(soc.L3CacheParamsOpt.isEmpty){
385    l3_out :*= l3_in
386  }
387
388  if (!enableCHI) {
389    for (port <- peripheral_ports.get) {
390      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
391    }
392  }
393
394  core_to_l3_ports.foreach { case _ =>
395    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
396      l3_banked_xbar.get :=*
397        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
398        TLBuffer() :=
399        core_out
400    }
401  }
402
403  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
404  if (enableCHI) { clint.node := device_xbar.get }
405  else { clint.node := peripheralXbar.get }
406
407  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
408    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
409    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
410      val in = IO(Input(Vec(num, Bool())))
411      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
412    }
413    lazy val module = new IntSourceNodeToModuleImp(this)
414  }
415
416  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
417  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
418
419  plic.intnode := plicSource.sourceNode
420  if (enableCHI) { plic.node := device_xbar.get }
421  else { plic.node := peripheralXbar.get }
422
423  val pll_node = TLRegisterNode(
424    address = Seq(soc.PLLRange),
425    device = new SimpleDevice("pll_ctrl", Seq()),
426    beatBytes = 8,
427    concurrency = 1
428  )
429  if (enableCHI) { pll_node := device_xbar.get }
430  else { pll_node := peripheralXbar.get }
431
432  val debugModule = LazyModule(new DebugModule(NumCores)(p))
433  if (enableCHI) {
434    debugModule.debug.node := device_xbar.get
435    // TODO: l3_xbar
436    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
437      error_xbar.get := sb2tl.node
438    }
439  } else {
440    debugModule.debug.node := peripheralXbar.get
441    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
442      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
443    }
444  }
445
446  val pma = LazyModule(new TLPMA)
447  if (enableCHI) {
448    pma.node := TLBuffer.chainNode(4) := device_xbar.get
449  } else {
450    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
451  }
452
453  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
454
455    val debug_module_io = IO(new debugModule.DebugModuleIO)
456    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
457    val rtc_clock = IO(Input(Bool()))
458    val pll0_lock = IO(Input(Bool()))
459    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
460    val cacheable_check = IO(new TLPMAIO)
461    val clintTime = IO(Output(ValidIO(UInt(64.W))))
462
463    debugModule.module.io <> debug_module_io
464
465    // sync external interrupts
466    require(plicSource.module.in.length == ext_intrs.getWidth)
467    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
468      val ext_intr_sync = RegInit(0.U(3.W))
469      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
470      plic_in := ext_intr_sync(2)
471    }
472
473    pma.module.io <> cacheable_check
474
475    // positive edge sampling of the lower-speed rtc_clock
476    val rtcTick = RegInit(0.U(3.W))
477    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
478    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
479
480    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
481    val pll_lock = RegNext(next = pll0_lock, init = false.B)
482
483    clintTime := clint.module.io.time
484
485    pll0_ctrl <> VecInit(pll_ctrl_regs)
486
487    pll_node.regmap(
488      0x000 -> RegFieldGroup(
489        "Pll", Some("PLL ctrl regs"),
490        pll_ctrl_regs.zipWithIndex.map{
491          case (r, i) => RegField(32, r, RegFieldDesc(
492            s"PLL_ctrl_$i",
493            desc = s"PLL ctrl register #$i"
494          ))
495        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
496          "PLL_lock",
497          "PLL lock register"
498        ))
499      )
500    )
501  }
502
503  lazy val module = new SoCMiscImp(this)
504}
505
506class SoCMisc()(implicit p: Parameters) extends MemMisc
507  with HaveSlaveAXI4Port
508
509