xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 94aa21c6009c2f39c5c5dae9c87260c78887efcc)
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.issue.EntryBundles._
11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.datapath.DataSource
14import xiangshan.backend.fu.{FuConfig, FuType}
15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
16import xiangshan.backend.rob.RobPtr
17import xiangshan.backend.datapath.NewPipelineConnect
18import xiangshan.backend.fu.vector.Bundles.VSew
19
20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
21  override def shouldBeInlined: Boolean = false
22
23  implicit val iqParams: IssueBlockParams = params
24  lazy val module: IssueQueueImp = iqParams.schdType match {
25    case IntScheduler() => new IssueQueueIntImp(this)
26    case FpScheduler() => new IssueQueueFpImp(this)
27    case VfScheduler() => new IssueQueueVfImp(this)
28    case MemScheduler() =>
29      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
30      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
31      else new IssueQueueIntImp(this)
32    case _ => null
33  }
34}
35
36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
37  val empty = Output(Bool())
38  val full = Output(Bool())
39  val validCnt = Output(UInt(log2Ceil(numEntries + 1).W))
40  val leftVec = Output(Vec(numEnq + 1, Bool()))
41}
42
43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
44
45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
46  // Inputs
47  val flush = Flipped(ValidIO(new Redirect))
48  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
49
50  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
55  val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
56  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle)
57  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle)
58  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
59  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
60  val wakeupFromWBDelayed: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
61  val wakeupFromIQDelayed: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
62  val vlFromIntIsZero = Input(Bool())
63  val vlFromIntIsVlmax = Input(Bool())
64  val vlFromVfIsZero = Input(Bool())
65  val vlFromVfIsVlmax = Input(Bool())
66  val og0Cancel = Input(ExuVec())
67  val og1Cancel = Input(ExuVec())
68  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
69  val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W))))
70
71  // Outputs
72  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
73  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
74  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
75  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
76
77  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
78  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
79}
80
81class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
82  extends LazyModuleImp(wrapper)
83  with HasXSParameter {
84
85  override def desiredName: String = s"${params.getIQName}"
86
87  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
88    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
89    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
90    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
91    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
92    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
93
94  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
95  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
96  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
97  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
98
99  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
100  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
101  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
102  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
103  val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap)
104
105  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}")
106  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
107  if (params.hasIQWakeUp) {
108    val exuSourcesEncodeString = params.wakeUpSourceExuIdx.map(x => 1 << x).reduce(_ + _).toBinaryString
109    println(s"[IssueQueueImp] ${params.getIQName} exuSourcesWidth: ${ExuSource().value.getWidth}, " +
110      s"exuSourcesEncodeMask: ${"0" * (p(XSCoreParamsKey).backendParams.numExu - exuSourcesEncodeString.length) + exuSourcesEncodeString}")
111  }
112
113  lazy val io = IO(new IssueQueueIO())
114
115  // Modules
116  val entries = Module(new Entries)
117  val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) }
118  val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) }
119  val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
120  val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) }
121  val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) }
122  val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) }
123  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
124  val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
125  val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) }
126  val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) }
127  val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) }
128  val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) }
129
130  class WakeupQueueFlush extends Bundle {
131    val redirect = ValidIO(new Redirect)
132    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
133    val og0Fail = Output(Bool())
134    val og1Fail = Output(Bool())
135  }
136
137  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
138    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
139    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
140    val ogFailFlush = stage match {
141      case 1 => flush.og0Fail
142      case 2 => flush.og1Fail
143      case _ => false.B
144    }
145    redirectFlush || loadDependencyFlush || ogFailFlush
146  }
147
148  private def modificationFunc(exuInput: ExuInput): ExuInput = {
149    val newExuInput = WireDefault(exuInput)
150    newExuInput.loadDependency match {
151      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
152      case None =>
153    }
154    newExuInput
155  }
156
157  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
158    val lastExuInput = WireDefault(exuInput)
159    val newExuInput = WireDefault(newInput)
160    newExuInput.elements.foreach { case (name, data) =>
161      if (lastExuInput.elements.contains(name)) {
162        data := lastExuInput.elements(name)
163      }
164    }
165    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
166      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
167    }
168    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
169      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
170    }
171    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
172      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
173    }
174    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
175      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get)
176    }
177    if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) {
178      newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get)
179    }
180    if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) {
181      newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get)
182    }
183    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
184      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
185    }
186    newExuInput
187  }
188
189  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module(
190    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
191  ))}
192  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
193
194  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
195  val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable)
196  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
197  val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable)
198  val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable)
199
200  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
201  val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable)
202  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
203  val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable)
204  val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable)
205
206  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
207  val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet)
208  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
209  val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet)
210  val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet)
211
212  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
213  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
214  val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
215  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
216  val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
217  val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
218
219  val s0_enqValidVec = io.enq.map(_.valid)
220  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
221  val s0_enqNotFlush = !io.flush.valid
222  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
223  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
224
225
226  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
227  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
228
229  val validVec = VecInit(entries.io.valid.asBools)
230  val issuedVec = VecInit(entries.io.issued.asBools)
231  val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2))
232  val canIssueVec = VecInit(entries.io.canIssue.asBools)
233  dontTouch(canIssueVec)
234  val deqFirstIssueVec = entries.io.isFirstIssue
235
236  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
237  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
238  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
239  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
240  // (entryIdx)(srcIdx)
241  val exuSources: Option[Vec[Vec[ExuSource]]] = entries.io.exuSources
242  // (deqIdx)(srcIdx)
243  val finalExuSources: Option[Vec[Vec[ExuSource]]] = exuSources.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
244
245  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
246  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
247  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
248  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
249
250  //deq
251  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
252  val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
253  val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
254  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
255  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
256  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
257  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
258
259  val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool())))
260  val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
261  val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W)))
262
263  //trans
264  val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
265  val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W))))
266  val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
267  val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
268  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
269
270  // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle
271  // as vf exu's min latency is 1, we do not need consider og0cancel
272  val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ))
273  wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) =>
274    if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) {
275      val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel)
276      w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w)))
277      w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) }
278    } else {
279      w := w_src
280    }
281  }
282  val wakeupFromIQDelayed = Wire(chiselTypeOf(io.wakeupFromIQDelayed))
283  wakeupFromIQDelayed.zip(io.wakeupFromIQDelayed).foreach { case (w, w_src) =>
284    if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) {
285      val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel)
286      w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w)))
287      w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach { case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) }
288    } else {
289      w := w_src
290    }
291  }
292
293  /**
294    * Connection of [[entries]]
295    */
296  entries.io match { case entriesIO: EntriesIO =>
297    entriesIO.flush                                             := io.flush
298    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
299      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
300      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
301      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
302      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
303      for(j <- 0 until numLsrc) {
304        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
305        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
306        enq.bits.status.srcStatus(j).srcState                   := (if (j < 3) {
307                                                                      Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
308                                                                          SrcState.rdy,
309                                                                          s0_enqBits(enqIdx).srcState(j))
310                                                                    } else {
311                                                                      s0_enqBits(enqIdx).srcState(j)
312                                                                    })
313        enq.bits.status.srcStatus(j).dataSources.value          := (if (j < 3) {
314                                                                      MuxCase(DataSource.reg, Seq(
315                                                                        (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero,
316                                                                        SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j))                                       -> DataSource.imm,
317                                                                        (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0,
318                                                                      ))
319                                                                    } else {
320                                                                      MuxCase(DataSource.reg, Seq(
321                                                                        SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j))  -> DataSource.imm,
322                                                                      ))
323                                                                    })
324        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1))
325        enq.bits.status.srcStatus(j).exuSources.foreach(_       := 0.U.asTypeOf(ExuSource()))
326        enq.bits.status.srcStatus(j).useRegCache.foreach(_      := s0_enqBits(enqIdx).useRegCache(j))
327        enq.bits.status.srcStatus(j).regCacheIdx.foreach(_      := s0_enqBits(enqIdx).regCacheIdx(j))
328      }
329      enq.bits.status.blocked                                   := false.B
330      enq.bits.status.issued                                    := false.B
331      enq.bits.status.firstIssue                                := false.B
332      enq.bits.status.issueTimer                                := "b11".U
333      enq.bits.status.deqPortIdx                                := 0.U
334      enq.bits.imm.foreach(_                                    := s0_enqBits(enqIdx).imm)
335      enq.bits.payload                                          := s0_enqBits(enqIdx)
336    }
337    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
338      og0Resp                                                   := io.og0Resp(i)
339    }
340    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
341      og1Resp                                                   := io.og1Resp(i)
342    }
343    if (params.needOg2Resp) {
344      entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) =>
345        og2Resp                                                 := io.og2Resp.get(i)
346      }
347    }
348    if (params.isLdAddrIQ || params.isHyAddrIQ) {
349      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
350        finalIssueResp                                          := io.finalIssueResp.get(i)
351      }
352      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
353        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
354      }
355    }
356    if (params.isVecLduIQ) {
357      entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) =>
358        resp := io.finalIssueResp.get(i)
359      }
360      entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) =>
361        resp                                                    := io.vecLoadIssueResp.get(i)
362      }
363    }
364    for(deqIdx <- 0 until params.numDeq) {
365      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
366      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
367      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
368      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
369      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
370      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
371      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
372      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
373      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
374    }
375    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
376    entriesIO.wakeUpFromIQ                                      := wakeupFromIQ
377    entriesIO.wakeUpFromWBDelayed                               := io.wakeupFromWBDelayed
378    entriesIO.wakeUpFromIQDelayed                               := wakeupFromIQDelayed
379    entriesIO.vlFromIntIsZero                                   := io.vlFromIntIsZero
380    entriesIO.vlFromIntIsVlmax                                  := io.vlFromIntIsVlmax
381    entriesIO.vlFromVfIsZero                                    := io.vlFromVfIsZero
382    entriesIO.vlFromVfIsVlmax                                   := io.vlFromVfIsVlmax
383    entriesIO.og0Cancel                                         := io.og0Cancel
384    entriesIO.og1Cancel                                         := io.og1Cancel
385    entriesIO.ldCancel                                          := io.ldCancel
386    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
387    //output
388    fuTypeVec                                                   := entriesIO.fuType
389    deqEntryVec                                                 := entriesIO.deqEntry
390    cancelDeqVec                                                := entriesIO.cancelDeqVec
391    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
392    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
393    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
394  }
395
396
397  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
398
399  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
400    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
401  ).reverse)
402
403  // if deq port can accept the uop
404  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
405    Cat(fuTypeVec.map(fuType =>
406      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
407    ).reverse)
408  }
409
410  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
411    fuTypeVec.map(fuType =>
412      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
413  }
414
415  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
416    val mergeFuBusy = {
417      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
418      else canIssueVec.asUInt
419    }
420    val mergeIntWbBusy = {
421      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
422      else mergeFuBusy
423    }
424    val mergefpWbBusy = {
425      if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i))
426      else mergeIntWbBusy
427    }
428    val mergeVfWbBusy = {
429      if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i))
430      else mergefpWbBusy
431    }
432    val mergeV0WbBusy = {
433      if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i))
434      else mergeVfWbBusy
435    }
436    val mergeVlWbBusy = {
437      if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i))
438      else  mergeV0WbBusy
439    }
440    merge := mergeVlWbBusy
441  }
442
443  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
444    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
445  }
446  dontTouch(fuTypeVec)
447  dontTouch(canIssueMergeAllBusy)
448  dontTouch(deqCanIssue)
449
450  if (params.numDeq == 2) {
451    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
452  }
453
454  if (params.numDeq == 2 && params.deqFuSame) {
455    val subDeqPolicy = Module(new DeqPolicy())
456
457    enqEntryOldestSel := DontCare
458
459    if (params.isAllComp || params.isAllSimp) {
460      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
461        enq = othersEntryEnqSelVec.get,
462        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
463      )
464      othersEntryOldestSel(1) := DontCare
465
466      subDeqPolicy.io.request := subDeqRequest.get
467      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
468      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
469    }
470    else {
471      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
472      simpAgeDetectRequest.get(1) := DontCare
473      simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt
474      if (params.numEnq == 2) {
475        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
476      }
477
478      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
479        enq = simpEntryEnqSelVec.get,
480        canIssue = simpAgeDetectRequest.get
481      )
482
483      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
484        enq = compEntryEnqSelVec.get,
485        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
486      )
487      compEntryOldestSel.get(1) := DontCare
488
489      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
490      othersEntryOldestSel(0).bits := Cat(
491        compEntryOldestSel.get(0).bits,
492        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
493      )
494      othersEntryOldestSel(1) := DontCare
495
496      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
497      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
498      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
499    }
500
501    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
502
503    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
504    deqSelValidVec(1) := subDeqSelValidVec.get(0)
505    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
506                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
507                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
508    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
509
510    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
511      selValid := deqValid && deqOH.orR
512      selOH := deqOH
513    }
514  }
515  else {
516    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
517      enq = VecInit(s0_doEnqSelValidVec),
518      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
519    )
520
521    if (params.isAllComp || params.isAllSimp) {
522      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
523        enq = othersEntryEnqSelVec.get,
524        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
525      )
526
527      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
528        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
529          selValid := false.B
530          selOH := 0.U.asTypeOf(selOH)
531        } else {
532          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
533          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
534        }
535      }
536    }
537    else {
538      othersEntryOldestSel := DontCare
539
540      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
541        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
542      }
543      simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt
544      if (params.numEnq == 2) {
545        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
546      }
547
548      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
549        enq = simpEntryEnqSelVec.get,
550        canIssue = simpAgeDetectRequest.get
551      )
552
553      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
554        enq = compEntryEnqSelVec.get,
555        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
556      )
557
558      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
559        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
560          selValid := false.B
561          selOH := 0.U.asTypeOf(selOH)
562        } else {
563          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
564          selOH := Cat(
565            compEntryOldestSel.get(i).bits,
566            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
567            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
568          )
569        }
570      }
571    }
572
573    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
574      selValid := deqValid
575      selOH := deqOH
576    }
577  }
578
579  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
580
581  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
582    deqResp.valid := deqBeforeDly(i).valid
583    deqResp.bits.resp   := RespType.success
584    deqResp.bits.robIdx := DontCare
585    deqResp.bits.sqIdx.foreach(_ := DontCare)
586    deqResp.bits.lqIdx.foreach(_ := DontCare)
587    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
588    deqResp.bits.uopIdx.foreach(_ := DontCare)
589  }
590
591  //fuBusyTable
592  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
593    if(busyTableWrite.nonEmpty) {
594      val btwr = busyTableWrite.get
595      val btrd = busyTableRead.get
596      btwr.io.in.deqResp := toBusyTableDeqResp(i)
597      btwr.io.in.og0Resp := io.og0Resp(i)
598      btwr.io.in.og1Resp := io.og1Resp(i)
599      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
600      btrd.io.in.fuTypeRegVec := fuTypeVec
601      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
602    }
603    else {
604      fuBusyTableMask(i) := 0.U(params.numEntries.W)
605    }
606  }
607
608  //wbfuBusyTable write
609  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
610    if(busyTableWrite.nonEmpty) {
611      val btwr = busyTableWrite.get
612      val bt = busyTable.get
613      val dq = deqResp.get
614      btwr.io.in.deqResp := toBusyTableDeqResp(i)
615      btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B)
616      btwr.io.in.og0Resp := io.og0Resp(i)
617      btwr.io.in.og1Resp := io.og1Resp(i)
618      bt := btwr.io.out.fuBusyTable
619      dq := btwr.io.out.deqRespSet
620    }
621  }
622
623  fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
624    if (busyTableWrite.nonEmpty) {
625      val btwr = busyTableWrite.get
626      val bt = busyTable.get
627      val dq = deqResp.get
628      btwr.io.in.deqResp := toBusyTableDeqResp(i)
629      btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B)
630      btwr.io.in.og0Resp := io.og0Resp(i)
631      btwr.io.in.og1Resp := io.og1Resp(i)
632      bt := btwr.io.out.fuBusyTable
633      dq := btwr.io.out.deqRespSet
634    }
635  }
636
637  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
638    if (busyTableWrite.nonEmpty) {
639      val btwr = busyTableWrite.get
640      val bt = busyTable.get
641      val dq = deqResp.get
642      btwr.io.in.deqResp := toBusyTableDeqResp(i)
643      btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B)
644      btwr.io.in.og0Resp := io.og0Resp(i)
645      btwr.io.in.og1Resp := io.og1Resp(i)
646      bt := btwr.io.out.fuBusyTable
647      dq := btwr.io.out.deqRespSet
648    }
649  }
650
651  v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
652    if (busyTableWrite.nonEmpty) {
653      val btwr = busyTableWrite.get
654      val bt = busyTable.get
655      val dq = deqResp.get
656      btwr.io.in.deqResp := toBusyTableDeqResp(i)
657      btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B)
658      btwr.io.in.og0Resp := io.og0Resp(i)
659      btwr.io.in.og1Resp := io.og1Resp(i)
660      bt := btwr.io.out.fuBusyTable
661      dq := btwr.io.out.deqRespSet
662    }
663  }
664
665  vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
666    if (busyTableWrite.nonEmpty) {
667      val btwr = busyTableWrite.get
668      val bt = busyTable.get
669      val dq = deqResp.get
670      btwr.io.in.deqResp := toBusyTableDeqResp(i)
671      btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B)
672      btwr.io.in.og0Resp := io.og0Resp(i)
673      btwr.io.in.og1Resp := io.og1Resp(i)
674      bt := btwr.io.out.fuBusyTable
675      dq := btwr.io.out.deqRespSet
676    }
677  }
678
679  //wbfuBusyTable read
680  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
681    if(busyTableRead.nonEmpty) {
682      val btrd = busyTableRead.get
683      val bt = busyTable.get
684      btrd.io.in.fuBusyTable := bt
685      btrd.io.in.fuTypeRegVec := fuTypeVec
686      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
687    }
688    else {
689      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
690    }
691  }
692  fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
693    if (busyTableRead.nonEmpty) {
694      val btrd = busyTableRead.get
695      val bt = busyTable.get
696      btrd.io.in.fuBusyTable := bt
697      btrd.io.in.fuTypeRegVec := fuTypeVec
698      fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
699    }
700    else {
701      fpWbBusyTableMask(i) := 0.U(params.numEntries.W)
702    }
703  }
704  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
705    if (busyTableRead.nonEmpty) {
706      val btrd = busyTableRead.get
707      val bt = busyTable.get
708      btrd.io.in.fuBusyTable := bt
709      btrd.io.in.fuTypeRegVec := fuTypeVec
710      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
711    }
712    else {
713      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
714    }
715  }
716  v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
717    if (busyTableRead.nonEmpty) {
718      val btrd = busyTableRead.get
719      val bt = busyTable.get
720      btrd.io.in.fuBusyTable := bt
721      btrd.io.in.fuTypeRegVec := fuTypeVec
722      v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
723    }
724    else {
725      v0WbBusyTableMask(i) := 0.U(params.numEntries.W)
726    }
727  }
728  vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
729    if (busyTableRead.nonEmpty) {
730      val btrd = busyTableRead.get
731      val bt = busyTable.get
732      btrd.io.in.fuBusyTable := bt
733      btrd.io.in.fuTypeRegVec := fuTypeVec
734      vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
735    }
736    else {
737      vlWbBusyTableMask(i) := 0.U(params.numEntries.W)
738    }
739  }
740
741  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
742    wakeUpQueueOption.foreach {
743      wakeUpQueue =>
744        val flush = Wire(new WakeupQueueFlush)
745        flush.redirect := io.flush
746        flush.ldCancel := io.ldCancel
747        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
748        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
749        wakeUpQueue.io.flush := flush
750        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
751        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
752        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
753        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
754    }
755  }
756
757  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
758    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
759    deq.bits.addrOH          := finalDeqSelOHVec(i)
760    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
761    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
762    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
763    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
764    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
765    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
766    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
767    deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen)
768    deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen)
769    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
770    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
771    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
772
773    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
774    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
775    deq.bits.common.exuSources.foreach(_.zip(finalExuSources.get(i)).foreach { case (sink, source) => sink := source})
776    deq.bits.common.srcTimer.foreach(_ := DontCare)
777    deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source})
778    deq.bits.common.src := DontCare
779    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
780
781    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
782      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
783      rf.foreach(_.addr := psrc)
784      rf.foreach(_.srcType := srcType)
785    }
786    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
787      sink := source
788    }
789    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
790    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
791    deq.bits.common.nextPcOffset.foreach(_ := 0.U)
792    deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get))
793
794    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
795    deq.bits.common.perfDebugInfo.selectTime := GTimer()
796    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
797  }
798
799  val deqDelay = Reg(params.genIssueValidBundle)
800  deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
801    deqDly.valid := deq.valid
802    when(validVec.asUInt.orR) {
803      deqDly.bits := deq.bits
804    }
805    // deqBeforeDly.ready is always true
806    deq.ready := true.B
807  }
808  io.deqDelay.zip(deqDelay).foreach { case (sink, source) =>
809    sink.valid := source.valid
810    sink.bits := source.bits
811  }
812  if(backendParams.debugEn) {
813    dontTouch(deqDelay)
814    dontTouch(io.deqDelay)
815    dontTouch(deqBeforeDly)
816  }
817  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
818    if (wakeUpQueues(i).nonEmpty) {
819      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
820      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
821      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
822      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
823      wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i))
824    } else {
825      wakeup.valid := false.B
826      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
827    }
828    if (wakeUpQueues(i).nonEmpty) {
829      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
830      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
831      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
832      wakeup.bits.v0Wen  := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B)
833      wakeup.bits.vlWen  := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B)
834    }
835
836    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
837      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
838    }
839    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
840      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
841    }
842    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
843      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
844    }
845    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
846      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
847    }
848    if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) {
849      wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get
850    }
851    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) {
852      wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get
853    }
854    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
855      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
856    }
857  }
858
859  // Todo: better counter implementation
860  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
861  private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _)
862  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
863  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
864  private val enqEntryValidCntDeq0 = PopCount(
865    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
866  )
867  private val othersValidCntDeq0 = PopCount(
868    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
869  )
870  private val enqEntryValidCntDeq1 = PopCount(
871    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
872  )
873  private val othersValidCntDeq1 = PopCount(
874    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
875  )
876  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
877    io.enq.map(_.bits.fuType).map(fuType =>
878      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
879  }
880  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
881  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
882  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
883  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
884  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
885  for (i <- 0 until params.numEnq) {
886    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
887  }
888  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
889  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
890    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
891  }
892  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
893  private val othersCanotIn = Wire(Bool())
894  othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
895  // if has simp Entry, othersCanotIn will be simpCanotIn
896  if (params.numSimp > 0) {
897    val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W)))
898    simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
899      leftone := ~(1.U((params.numSimp).W) << i)
900    }
901    val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _)
902    val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _)
903    othersCanotIn := simpCanotIn
904  }
905  io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued)
906  io.status.empty := !Cat(validVec).orR
907  io.status.full := othersCanotIn
908  io.status.validCnt := PopCount(validVec)
909
910  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
911    Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
912  }
913
914  // issue perf counter
915  // enq count
916  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
917  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
918  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
919  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
920  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
921  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
922  // valid count
923  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
924  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
925  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
926  // only split when more than 1 func type
927  if (params.getFuCfgs.size > 0) {
928    for (t <- FuType.functionNameMap.keys) {
929      val fuName = FuType.functionNameMap(t)
930      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
931        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
932      }
933    }
934  }
935  // ready instr count
936  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
937  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
938  // only split when more than 1 func type
939  if (params.getFuCfgs.size > 0) {
940    for (t <- FuType.functionNameMap.keys) {
941      val fuName = FuType.functionNameMap(t)
942      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
943        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
944      }
945    }
946  }
947
948  // deq instr count
949  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
950  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
951  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
952  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
953
954  // deq instr data source count
955  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
956    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
957  }.reduce(_ +& _))
958  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
959    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
960  }.reduce(_ +& _))
961  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
962    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
963  }.reduce(_ +& _))
964  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
965    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
966  }.reduce(_ +& _))
967
968  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
969    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
970  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
971  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
972    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
973  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
974  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
975    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
976  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
977  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
978    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
979  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
980
981  // deq instr data source count for each futype
982  for (t <- FuType.functionNameMap.keys) {
983    val fuName = FuType.functionNameMap(t)
984    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
985      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
986        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
987      }.reduce(_ +& _))
988      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
989        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
990      }.reduce(_ +& _))
991      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
992        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
993      }.reduce(_ +& _))
994      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
995        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
996      }.reduce(_ +& _))
997
998      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
999        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
1000      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
1001      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
1002        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
1003      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
1004      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
1005        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
1006      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
1007      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
1008        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
1009      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
1010    }
1011  }
1012}
1013
1014class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
1015  val fastMatch = UInt(backendParams.LduCnt.W)
1016  val fastImm = UInt(12.W)
1017}
1018
1019class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
1020
1021class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
1022  extends IssueQueueImp(wrapper)
1023{
1024  io.suggestName("none")
1025  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
1026
1027  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
1028    deq.bits.common.pc.foreach(_ := DontCare)
1029    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
1030    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
1031    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
1032    deq.bits.common.predictInfo.foreach(x => {
1033      x.target := DontCare
1034      x.taken := deqEntryVec(i).bits.payload.pred_taken
1035    })
1036    // for std
1037    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
1038    // for i2f
1039    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1040  }}
1041}
1042
1043class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
1044  extends IssueQueueImp(wrapper)
1045{
1046  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
1047    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1048    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1049    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1050    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1051  }}
1052}
1053
1054class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
1055  extends IssueQueueImp(wrapper)
1056{
1057  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
1058    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1059    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1060    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1061    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1062  }}
1063}
1064
1065class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
1066  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ)))
1067
1068  // TODO: is still needed?
1069  val checkWait = new Bundle {
1070    val stIssuePtr = Input(new SqPtr)
1071    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
1072  }
1073  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
1074
1075  // load wakeup
1076  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
1077
1078  // vector
1079  val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr))
1080  val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr))
1081}
1082
1083class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
1084  val memIO = Some(new IssueQueueMemBundle)
1085}
1086
1087class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
1088  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
1089
1090  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
1091    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
1092  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
1093
1094  io.suggestName("none")
1095  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
1096  private val memIO = io.memIO.get
1097
1098  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
1099
1100  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1101    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
1102    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1103    slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx)
1104    slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx)
1105    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1106    slowResp.bits.fuType := DontCare
1107  }
1108
1109  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1110    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
1111    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1112    fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx)
1113    fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx)
1114    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1115    fastResp.bits.fuType := DontCare
1116  }
1117
1118  // load wakeup
1119  val loadWakeUpIter = memIO.loadWakeUp.iterator
1120  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
1121    if (param.hasLoadExu) {
1122      require(wakeUpQueues(i).isEmpty)
1123      val uop = loadWakeUpIter.next()
1124
1125      wakeup.valid := GatedValidRegNext(uop.fire)
1126      wakeup.bits.rfWen  := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen  && uop.fire) else false.B)
1127      wakeup.bits.fpWen  := (if (params.writeFpRf)  GatedValidRegNext(uop.bits.fpWen  && uop.fire) else false.B)
1128      wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B)
1129      wakeup.bits.v0Wen  := (if (params.writeV0Rf)  GatedValidRegNext(uop.bits.v0Wen  && uop.fire) else false.B)
1130      wakeup.bits.vlWen  := (if (params.writeVlRf)  GatedValidRegNext(uop.bits.vlWen  && uop.fire) else false.B)
1131      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
1132      wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i))
1133      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
1134
1135      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen  && uop.fire) else false.B)))
1136      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf)  GatedValidRegNext(uop.bits.fpWen  && uop.fire) else false.B)))
1137      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B)))
1138      wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf)  GatedValidRegNext(uop.bits.v0Wen  && uop.fire) else false.B)))
1139      wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf)  GatedValidRegNext(uop.bits.vlWen  && uop.fire) else false.B)))
1140      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
1141      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
1142
1143      wakeup.bits.is0Lat := 0.U
1144    }
1145  }
1146  require(!loadWakeUpIter.hasNext)
1147
1148  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1149    deq.bits.common.pc.foreach(_ := 0.U)
1150    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
1151    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
1152    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
1153    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
1154    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
1155    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
1156    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
1157    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
1158    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
1159  }
1160}
1161
1162class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
1163  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
1164
1165  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
1166  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
1167
1168  io.suggestName("none")
1169  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
1170  private val memIO = io.memIO.get
1171
1172  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
1173
1174  for (i <- entries.io.enq.indices) {
1175    entries.io.enq(i).bits.status match { case enqData =>
1176      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
1177      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
1178      // MemAddrIQ also handle vector insts
1179      enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
1180
1181      val isFirstLoad           = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get
1182      val isVleff               = s0_enqBits(i).vpu.isVleff
1183      enqData.blocked          := !isFirstLoad && isVleff
1184    }
1185  }
1186
1187  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1188    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1189    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1190    slowResp.bits.sqIdx.get        := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx
1191    slowResp.bits.lqIdx.get        := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx
1192    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1193    slowResp.bits.fuType           := DontCare
1194    slowResp.bits.uopIdx.get       := DontCare
1195  }
1196
1197  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1198    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1199    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1200    fastResp.bits.sqIdx.get        := memIO.feedbackIO(i).feedbackFast.bits.sqIdx
1201    fastResp.bits.lqIdx.get        := memIO.feedbackIO(i).feedbackFast.bits.lqIdx
1202    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1203    fastResp.bits.fuType           := DontCare
1204    fastResp.bits.uopIdx.get       := DontCare
1205  }
1206
1207  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1208  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1209
1210  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1211    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1212    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1213    deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem)
1214    if (params.isVecLduIQ) {
1215      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1216      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1217    }
1218    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1219    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1220    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1221    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1222  }
1223
1224  io.vecLoadIssueResp.foreach(dontTouch(_))
1225}
1226