| e43bb916 | 20-Sep-2024 |
Xuan Hu <[email protected]> |
feat(VecLoad): add VecLoadExcp module to handle merging old/new data
* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg
feat(VecLoad): add VecLoadExcp module to handle merging old/new data
* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.
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