1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath._ 31import xiangshan.backend.dispatch.CoreDispatchTopDownIO 32import xiangshan.backend.exu.ExuBlock 33import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 34import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 35import xiangshan.backend.issue.EntryBundles._ 36import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 37import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 38import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 39import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 40import scala.collection.mutable 41 42class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 43 with HasXSParameter { 44 45 override def shouldBeInlined: Boolean = false 46 47 // check read & write port config 48 params.configChecks 49 50 /* Only update the idx in mem-scheduler here 51 * Idx in other schedulers can be updated the same way if needed 52 * 53 * Also note that we filter out the 'stData issue-queues' when counting 54 */ 55 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 56 ibp.updateIdx(idx) 57 } 58 59 println(params.iqWakeUpParams) 60 61 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 62 schdCfg.bindBackendParam(params) 63 } 64 65 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 66 iqCfg.bindBackendParam(params) 67 } 68 69 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 70 exuCfg.bindBackendParam(params) 71 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 72 exuCfg.updateExuIdx(i) 73 } 74 75 println("[Backend] ExuConfigs:") 76 for (exuCfg <- params.allExuParams) { 77 val fuConfigs = exuCfg.fuConfigs 78 val wbPortConfigs = exuCfg.wbPortConfigs 79 val immType = exuCfg.immType 80 81 println("[Backend] " + 82 s"${exuCfg.name}: " + 83 (if (exuCfg.fakeUnit) "fake, " else "") + 84 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 85 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 86 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 87 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 88 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 89 s"srcReg(${exuCfg.numRegSrc})" 90 ) 91 require( 92 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 93 fuConfigs.map(_.writeIntRf).reduce(_ || _), 94 s"${exuCfg.name} int wb port has no priority" 95 ) 96 require( 97 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 98 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 99 s"${exuCfg.name} vec wb port has no priority" 100 ) 101 } 102 103 println(s"[Backend] all fu configs") 104 for (cfg <- FuConfig.allConfigs) { 105 println(s"[Backend] $cfg") 106 } 107 108 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 109 for ((port, seq) <- params.getRdPortParams(IntData())) { 110 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 111 } 112 113 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 114 for ((port, seq) <- params.getWbPortParams(IntData())) { 115 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 116 } 117 118 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 119 for ((port, seq) <- params.getRdPortParams(VecData())) { 120 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 121 } 122 123 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 124 for ((port, seq) <- params.getWbPortParams(VecData())) { 125 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 126 } 127 128 println(s"[Backend] Dispatch Configs:") 129 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 130 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 131 132 params.updateCopyPdestInfo 133 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 134 params.allExuParams.map(_.copyNum) 135 val ctrlBlock = LazyModule(new CtrlBlock(params)) 136 val pcTargetMem = LazyModule(new PcTargetMem(params)) 137 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 138 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 139 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 140 val dataPath = LazyModule(new DataPath(params)) 141 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 142 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 143 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 144 145 lazy val module = new BackendImp(this) 146} 147 148class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 149 with HasXSParameter { 150 implicit private val params = wrapper.params 151 152 val io = IO(new BackendIO()(p, wrapper.params)) 153 154 private val ctrlBlock = wrapper.ctrlBlock.module 155 private val pcTargetMem = wrapper.pcTargetMem.module 156 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 157 private val vfScheduler = wrapper.vfScheduler.get.module 158 private val memScheduler = wrapper.memScheduler.get.module 159 private val dataPath = wrapper.dataPath.module 160 private val intExuBlock = wrapper.intExuBlock.get.module 161 private val vfExuBlock = wrapper.vfExuBlock.get.module 162 private val og2ForVector = Module(new Og2ForVector(params)) 163 private val bypassNetwork = Module(new BypassNetwork) 164 private val wbDataPath = Module(new WbDataPath(params)) 165 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 166 167 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 168 intScheduler.io.toSchedulers.wakeupVec ++ 169 vfScheduler.io.toSchedulers.wakeupVec ++ 170 memScheduler.io.toSchedulers.wakeupVec 171 ).map(x => (x.bits.exuIdx, x)).toMap 172 173 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 174 175 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 176 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 177 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 178 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 179 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 180 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 181 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 182 183 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 184 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 185 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 186 private val vlIsZero = intExuBlock.io.vlIsZero.get 187 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 188 189 ctrlBlock.io.IQValidNumVec := intScheduler.io.IQValidNumVec 190 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 191 ctrlBlock.io.frontend <> io.frontend 192 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 193 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 194 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 195 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 196 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 197 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 198 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 199 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 200 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 201 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 202 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 203 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 204 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 205 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 206 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 207 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 208 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 209 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 210 211 intScheduler.io.fromTop.hartId := io.fromTop.hartId 212 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 213 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 214 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 215 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 216 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 217 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 218 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 219 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 220 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 221 intScheduler.io.ldCancel := io.mem.ldCancel 222 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 223 intScheduler.io.vlWriteBack.vlIsZero := false.B 224 intScheduler.io.vlWriteBack.vlIsVlmax := false.B 225 226 memScheduler.io.fromTop.hartId := io.fromTop.hartId 227 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 228 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 229 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 230 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 231 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 232 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 233 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 234 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 235 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 236 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 237 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 238 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 239 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 240 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 241 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 242 sink.valid := source.valid 243 sink.bits := source.bits.robIdx 244 } 245 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 246 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 247 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 248 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 249 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 250 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 251 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 252 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 253 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 254 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 255 memScheduler.io.ldCancel := io.mem.ldCancel 256 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 257 memScheduler.io.vlWriteBack.vlIsZero := vlIsZero 258 memScheduler.io.vlWriteBack.vlIsVlmax := vlIsVlmax 259 260 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 261 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 262 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 263 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 264 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 265 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 266 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 267 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 268 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 269 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 270 vfScheduler.io.ldCancel := io.mem.ldCancel 271 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 272 vfScheduler.io.vlWriteBack.vlIsZero := vlIsZero 273 vfScheduler.io.vlWriteBack.vlIsVlmax := vlIsVlmax 274 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 275 276 dataPath.io.hartId := io.fromTop.hartId 277 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 278 279 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 280 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 281 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 282 283 dataPath.io.ldCancel := io.mem.ldCancel 284 285 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 286 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 287 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 288 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 289 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 290 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 291 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 292 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 293 294 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 295 og2ForVector.io.ldCancel := io.mem.ldCancel 296 og2ForVector.io.fromOg1NoReg <> dataPath.io.toFpExu 297 298 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 299 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 300 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 301 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 302 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 303 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 304 305 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 306 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 307 s"io.mem.writeback(${io.mem.writeBack.size})" 308 ) 309 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 310 sink.valid := source.valid 311 sink.bits.pdest := source.bits.uop.pdest 312 sink.bits.data := source.bits.data 313 } 314 315 316 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 317 for (i <- 0 until intExuBlock.io.in.length) { 318 for (j <- 0 until intExuBlock.io.in(i).length) { 319 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 320 NewPipelineConnect( 321 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 322 Mux( 323 bypassNetwork.io.toExus.int(i)(j).fire, 324 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 325 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 326 ), 327 Option("intExuBlock2bypassNetwork") 328 ) 329 } 330 } 331 332 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 333 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 334 335 private val csrio = intExuBlock.io.csrio.get 336 csrio.hartId := io.fromTop.hartId 337 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 338 csrio.fpu.isIllegal := false.B // Todo: remove it 339 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 340 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 341 342 val vsetvlVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf(new VType)) 343 ctrlBlock.io.robio.vsetvlVType := vsetvlVType 344 345 val debugVconfig = dataPath.io.debugVconfig match { 346 case Some(x) => dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 347 case None => 0.U.asTypeOf(new VConfig) 348 } 349 val commitVType = ctrlBlock.io.robio.commitVType.vtype 350 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 351 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 352 val debugVl = debugVconfig.vl 353 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 354 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 355 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 356 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 357 //Todo here need change design 358 csrio.vpu.set_vtype.valid := commitVType.valid 359 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 360 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 361 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 362 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 363 csrio.exception := ctrlBlock.io.robio.exception 364 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 365 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 366 csrio.externalInterrupt := io.fromTop.externalInterrupt 367 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 368 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 369 csrio.perf <> io.perf 370 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 371 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 372 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 373 private val fenceio = intExuBlock.io.fenceio.get 374 io.fenceio <> fenceio 375 fenceio.disableSfence := csrio.disableSfence 376 fenceio.disableHfenceg := csrio.disableHfenceg 377 fenceio.disableHfencev := csrio.disableHfencev 378 fenceio.virtMode := csrio.customCtrl.virtMode 379 380 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 381 for (i <- 0 until vfExuBlock.io.in.size) { 382 for (j <- 0 until vfExuBlock.io.in(i).size) { 383 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 384 NewPipelineConnect( 385 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 386 Mux( 387 bypassNetwork.io.toExus.vf(i)(j).fire, 388 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 389 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 390 ), 391 Option("vfExuBlock2bypassNetwork") 392 ) 393 394 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 395 } 396 } 397 398 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 399 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 400 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 401 402 wbDataPath.io.flush := ctrlBlock.io.redirect 403 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 404 wbDataPath.io.fromIntExu <> intExuBlock.io.out 405 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 406 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 407 sink.valid := source.valid 408 source.ready := sink.ready 409 sink.bits.data := source.bits.data 410 sink.bits.pdest := source.bits.uop.pdest 411 sink.bits.robIdx := source.bits.uop.robIdx 412 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 413 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 414 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 415 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 416 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 417 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 418 sink.bits.debug := source.bits.debug 419 sink.bits.debugInfo := source.bits.uop.debugInfo 420 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 421 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 422 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 423 sink.bits.vls.foreach(x => { 424 x.vdIdx := source.bits.vdIdx.get 425 x.vdIdxInField := source.bits.vdIdxInField.get 426 x.vpu := source.bits.uop.vpu 427 x.oldVdPsrc := source.bits.uop.psrc(2) 428 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 429 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 430 }) 431 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 432 } 433 434 // to mem 435 private val memIssueParams = params.memSchdParams.get.issueBlockParams 436 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 437 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 438 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 439 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 440 441 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 442 for (i <- toMem.indices) { 443 for (j <- toMem(i).indices) { 444 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 445 val issueTimeout = 446 if (memExuBlocksHasLDU(i)(j)) 447 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 448 else 449 false.B 450 451 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 452 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 453 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 454 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 455 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 456 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 457 } 458 459 NewPipelineConnect( 460 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 461 Mux( 462 bypassNetwork.io.toExus.mem(i)(j).fire, 463 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 464 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 465 ), 466 Option("bypassNetwork2toMemExus") 467 ) 468 469 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 470 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 471 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 472 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 473 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 474 } 475 476 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 477 memScheduler.io.vecLoadIssueResp(i)(j) match { 478 case resp => 479 resp.valid := toMem(i)(j).fire && LSUOpType.isVecLd(toMem(i)(j).bits.fuOpType) 480 resp.bits.fuType := toMem(i)(j).bits.fuType 481 resp.bits.robIdx := toMem(i)(j).bits.robIdx 482 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 483 resp.bits.resp := RespType.success 484 } 485 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 486 } 487 } 488 } 489 490 io.mem.redirect := ctrlBlock.io.redirect 491 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 492 val enableMdp = Constantin.createRecord("EnableMdp", true.B)(0) 493 sink.valid := source.valid 494 source.ready := sink.ready 495 sink.bits.iqIdx := source.bits.iqIdx 496 sink.bits.isFirstIssue := source.bits.isFirstIssue 497 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 498 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 499 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 500 sink.bits.uop.fuType := source.bits.fuType 501 sink.bits.uop.fuOpType := source.bits.fuOpType 502 sink.bits.uop.imm := source.bits.imm 503 sink.bits.uop.robIdx := source.bits.robIdx 504 sink.bits.uop.pdest := source.bits.pdest 505 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 506 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 507 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 508 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 509 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 510 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 511 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 512 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 513 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 514 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 515 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 516 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 517 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 518 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 519 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 520 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 521 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 522 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 523 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 524 } 525 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 526 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 527 io.mem.tlbCsr := csrio.tlb 528 io.mem.csrCtrl := csrio.customCtrl 529 io.mem.sfence := fenceio.sfence 530 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 531 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 532 require(io.mem.loadPcRead.size == params.LduCnt) 533 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 534 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 535 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 536 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 537 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 538 } 539 540 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 541 storePcRead := ctrlBlock.io.memStPcRead(i).data 542 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 543 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 544 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 545 } 546 547 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 548 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 549 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 550 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 551 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 552 }) 553 554 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 555 556 // mem io 557 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 558 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 559 560 io.frontendSfence := fenceio.sfence 561 io.frontendTlbCsr := csrio.tlb 562 io.frontendCsrCtrl := csrio.customCtrl 563 564 io.tlb <> csrio.tlb 565 566 io.csrCustomCtrl := csrio.customCtrl 567 568 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 569 570 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 571 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 572 573 io.debugRolling := ctrlBlock.io.debugRolling 574 575 if(backendParams.debugEn) { 576 dontTouch(memScheduler.io) 577 dontTouch(dataPath.io.toMemExu) 578 dontTouch(wbDataPath.io.fromMemExu) 579 } 580} 581 582class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 583 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 584 val flippedLda = true 585 // params alias 586 private val LoadQueueSize = VirtualLoadQueueSize 587 // In/Out // Todo: split it into one-direction bundle 588 val lsqEnqIO = Flipped(new LsqEnqIO) 589 val robLsqIO = new RobLsqIO 590 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 591 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 592 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 593 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 594 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 595 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 596 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 597 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 598 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 599 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 600 // Input 601 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 602 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 603 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 604 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 605 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 606 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 607 608 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 609 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 610 val memoryViolation = Flipped(ValidIO(new Redirect)) 611 val exceptionAddr = Input(new Bundle { 612 val vaddr = UInt(VAddrBits.W) 613 val gpaddr = UInt(GPAddrBits.W) 614 }) 615 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 616 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 617 val sqDeqPtr = Input(new SqPtr) 618 val lqDeqPtr = Input(new LqPtr) 619 620 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 621 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 622 623 val lqCanAccept = Input(Bool()) 624 val sqCanAccept = Input(Bool()) 625 626 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 627 val stIssuePtr = Input(new SqPtr()) 628 629 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 630 631 val debugLS = Flipped(Output(new DebugLSIO)) 632 633 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 634 // Output 635 val redirect = ValidIO(new Redirect) // rob flush MemBlock 636 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 637 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 638 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 639 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 640 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 641 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 642 643 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 644 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 645 646 val tlbCsr = Output(new TlbCsrBundle) 647 val csrCtrl = Output(new CustomCSRCtrlIO) 648 val sfence = Output(new SfenceBundle) 649 val isStoreException = Output(Bool()) 650 val isVlsException = Output(Bool()) 651 652 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 653 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 654 issueSta ++ 655 issueHylda ++ issueHysta ++ 656 issueLda ++ 657 issueVldu ++ 658 issueStd 659 }.toSeq 660 661 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 662 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 663 writebackSta ++ 664 writebackHyuLda ++ writebackHyuSta ++ 665 writebackLda ++ 666 writebackVldu ++ 667 writebackStd 668 } 669} 670 671class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 672 val fromTop = new Bundle { 673 val hartId = Input(UInt(hartIdLen.W)) 674 val externalInterrupt = new ExternalInterruptIO 675 } 676 677 val toTop = new Bundle { 678 val cpuHalted = Output(Bool()) 679 } 680 681 val fenceio = new FenceIO 682 // Todo: merge these bundles into BackendFrontendIO 683 val frontend = Flipped(new FrontendToCtrlIO) 684 val frontendSfence = Output(new SfenceBundle) 685 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 686 val frontendTlbCsr = Output(new TlbCsrBundle) 687 // distributed csr write 688 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 689 690 val mem = new BackendMemIO 691 692 val perf = Input(new PerfCounterIO) 693 694 val tlb = Output(new TlbCsrBundle) 695 696 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 697 698 val debugTopDown = new Bundle { 699 val fromRob = new RobCoreTopDownIO 700 val fromCore = new CoreDispatchTopDownIO 701 } 702 val debugRolling = new RobDebugRollingIO 703} 704