1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper, XSError} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 54 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 55 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 56 } 57 58 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 59 val sqIdx = new SqPtr 60 val lqIdx = new LqPtr 61 val numLsElem = NumLsElem() 62 } 63 64 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 65 val robIdx = new RobPtr 66 val resp = RespType() 67 val fuType = FuType() 68 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 69 } 70 71 object RespType { 72 def apply() = UInt(2.W) 73 74 def isBlocked(resp: UInt) = { 75 resp === block 76 } 77 78 def succeed(resp: UInt) = { 79 resp === success 80 } 81 82 val block = "b00".U 83 val uncertain = "b01".U 84 val success = "b11".U 85 } 86 87 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 88 val status = new Status() 89 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 90 val payload = new DynInst() 91 } 92 93 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 94 val flush = Flipped(ValidIO(new Redirect)) 95 val enq = Flipped(ValidIO(new EntryBundle)) 96 //wakeup 97 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 98 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 99 //cancel 100 val og0Cancel = Input(ExuOH(backendParams.numExu)) 101 val og1Cancel = Input(ExuOH(backendParams.numExu)) 102 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 103 //deq sel 104 val deqSel = Input(Bool()) 105 val deqPortIdxWrite = Input(UInt(1.W)) 106 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 107 //trans sel 108 val transSel = Input(Bool()) 109 // vector mem only 110 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 111 val sqDeqPtr = Input(new SqPtr) 112 val lqDeqPtr = Input(new LqPtr) 113 }) 114 } 115 116 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 117 //status 118 val valid = Output(Bool()) 119 val canIssue = Output(Bool()) 120 val fuType = Output(FuType()) 121 val robIdx = Output(new RobPtr) 122 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 123 //src 124 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 125 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 126 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 127 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val deqPortIdxRead = Output(UInt(1.W)) 132 val issueTimerRead = Output(UInt(2.W)) 133 //trans 134 val enqReady = Output(Bool()) 135 val transEntry = ValidIO(new EntryBundle) 136 // debug 137 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 138 val entryInValid = Output(Bool()) 139 val entryOutDeqValid = Output(Bool()) 140 val entryOutTransValid = Output(Bool()) 141 } 142 143 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 144 val validRegNext = Bool() 145 val flushed = Bool() 146 val clear = Bool() 147 val canIssue = Bool() 148 val enqReady = Bool() 149 val deqSuccess = Bool() 150 val srcWakeup = Vec(params.numRegSrc, Bool()) 151 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 152 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 153 val srcCancelVec = Vec(params.numRegSrc, Bool()) 154 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 155 } 156 157 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 158 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 159 common.flushed := status.robIdx.needFlush(commonIn.flush) 160 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 161 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 162 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 163 common.canIssue := validReg && status.canIssue 164 common.enqReady := !validReg || common.clear 165 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 166 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 167 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 168 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 169 srcCancel := srcLoadCancel || ldTransCancel 170 } 171 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 172 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 173 if(params.hasIQWakeUp) { 174 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 175 } else { 176 loadDependencyOut := loadDependency 177 } 178 179 } 180 if(isEnq) { 181 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 182 } else { 183 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 184 } 185 } 186 187 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 188 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 189 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 190 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 191 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 192 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 193 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 194 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 195 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 196 val cancelVec = Vec(params.numRegSrc, Bool()) 197 val canIssueBypass = Bool() 198 } 199 200 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 201 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 202 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 203 ).toSeq.transpose 204 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 205 206 hasIQWakeupGet.cancelVec := common.srcCancelVec 207 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 208 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 209 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 210 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 211 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 212 case (exuOH, regExuOH) => 213 exuOH := 0.U.asTypeOf(exuOH) 214 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 215 } 216 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 217 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 218 if(isEnq) { 219 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 220 } else { 221 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 222 } 223 } 224 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 225 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 226 wakeupVec.asUInt.orR | state 227 }).asUInt.andR 228 } 229 230 231 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 232 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 233 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 234 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 235 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 236 case ((dep, originalDep), deqPortIdx) => 237 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 238 dep := (originalDep << 2).asUInt | 2.U 239 else 240 dep := originalDep << 1 241 } 242 } 243 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 244 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 245 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 246 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 247 case ((dep, originalDep), deqPortIdx) => 248 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 249 dep := (originalDep << 1).asUInt | 1.U 250 else 251 dep := originalDep 252 } 253 } 254 } 255 256 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 257 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 258 val cancelByLd = common.srcCancelVec.asUInt.orR 259 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 260 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 261 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 262 entryUpdate.status.robIdx := status.robIdx 263 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 264 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 265 val cancel = common.srcCancelVec(srcIdx) 266 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 267 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 268 val wakeup = common.srcWakeup(srcIdx) 269 srcStatusNext.psrc := srcStatus.psrc 270 srcStatusNext.srcType := srcStatus.srcType 271 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 272 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, Mux(srcStatus.dataSources.readBypass, DataSource.reg, srcStatus.dataSources.value)) 273 if(params.hasIQWakeUp) { 274 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 275 // T0: waked up by IQ, T1: reset timer as 1 276 wakeupByIQ -> 2.U, 277 // do not overflow 278 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 279 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 280 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 281 )) 282 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 283 srcStatusNext.srcLoadDependency := 284 Mux(wakeup, 285 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 286 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 287 } else { 288 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 289 } 290 } 291 entryUpdate.status.blocked := false.B 292 entryUpdate.status.issued := MuxCase(status.issued, Seq( 293 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 294 commonIn.deqSel -> true.B, 295 !status.srcReady -> false.B, 296 )) 297 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 298 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 299 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 300 entryUpdate.imm.foreach(_ := entryReg.imm.get) 301 entryUpdate.payload := entryReg.payload 302 if (params.isVecMemIQ) { 303 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 304 } 305 } 306 307 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 308 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 309 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 310 commonOut.valid := validReg 311 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 312 else common.canIssue && !common.flushed) 313 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 314 commonOut.robIdx := status.robIdx 315 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 316 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 317 } 318 commonOut.isFirstIssue := !status.firstIssue 319 commonOut.entry.valid := validReg 320 commonOut.entry.bits := entryReg 321 if(isEnq) { 322 commonOut.entry.bits.status := status 323 } 324 commonOut.issueTimerRead := status.issueTimer 325 commonOut.deqPortIdxRead := status.deqPortIdx 326 if(params.hasIQWakeUp) { 327 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 328 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 329 else VecInit(srcWakeupExuOH)) 330 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 331 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 332 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 333 } 334 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 335 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 336 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 337 status.srcStatus(srcIdx).srcLoadDependency) 338 else status.srcStatus(srcIdx).srcLoadDependency) 339 } 340 } else { 341 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 342 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 343 } 344 } 345 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 346 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 347 common.srcLoadDependencyOut(srcIdx), 348 status.srcStatus(srcIdx).srcLoadDependency) 349 else status.srcStatus(srcIdx).srcLoadDependency) 350 } 351 commonOut.enqReady := common.enqReady 352 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 353 commonOut.transEntry.bits := entryUpdate 354 // debug 355 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 356 commonOut.entryInValid := commonIn.enq.valid 357 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 358 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 359 if (params.isVecMemIQ) { 360 commonOut.uopIdx.get := entryReg.payload.uopIdx 361 } 362 } 363 364 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 365 val fromLsq = commonIn.fromLsq.get 366 val vecMemStatus = entryReg.status.vecMem.get 367 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 368 vecMemStatusUpdate := vecMemStatus 369 370 val isLsqHead = { 371 entryReg.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 372 entryReg.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 373 } 374 375 // update blocked 376 entryUpdate.status.blocked := !isLsqHead // Todo: remove this 377 } 378 379 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 380 val origExuOH = 0.U.asTypeOf(exuOH) 381 when(wakeupByIQOH.asUInt.orR) { 382 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 383 }.otherwise { 384 origExuOH := regSrcExuOH 385 } 386 exuOH := 0.U.asTypeOf(exuOH) 387 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 388 } 389 390 object IQFuType { 391 def num = FuType.num 392 393 def apply() = Vec(num, Bool()) 394 395 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 396 val res = 0.U.asTypeOf(fuType) 397 fus.foreach(x => res(x.id) := fuType(x.id)) 398 res 399 } 400 } 401} 402