style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different instructions may have same fuoptype, so we need to check
both futype and fuoptype to distinguish the instructions

show more ...

busytable: support eliminate old vd when read vl's state

fix(IssueQueue, BusyTable): refactor wakeup and cancel, and remove redundant logic

feat(fof): let fof vector load uop always need oldvd wakeup

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

timing(Backend): add OG2 stage for vector mem (#3482)

IssueQueue: only trans valid but not issued entry for fix ldCancel timing

IssueQueue: enqReady remove deqSuccess and flushed for fix timing

Dispatch2Iq, IssueQueue: only int src data can read reg cache

IssueQueue: receive rcIdx from wakeup, add new data source type regcache

Backend: optimize og0 cancel signals (#3235)

* use Vec[Bool] instead of UInt for og0Cancel
* only wakeup source Exus containing 0-latency function unit should send
og0Cancel

chore: bump chisel 6.5.0 (#3210)

IssueQueue: fix bug of segment instruction which lqidx and sqidx are same (#3205)

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

show more ...

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

Backend: remove loadCancel from dispatch2iq to enqEntry for fix timing (#3105)

Entries: optimize timing of mem IQs' response signals (#3088)

IssueQueue: support v0 & vl split

Merge branch 'master' into vlsu-tmp-master

rv64v: ignore oldvd only when read vector register