1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16 17object EntryBundles extends HasCircularQueuePtrHelper { 18 19 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 20 //basic status 21 val robIdx = new RobPtr 22 val fuType = IQFuType() 23 //src status 24 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 25 //issue status 26 val blocked = Bool() 27 val issued = Bool() 28 val firstIssue = Bool() 29 val issueTimer = UInt(2.W) 30 val deqPortIdx = UInt(1.W) 31 //vector mem status 32 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 55 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 56 } 57 58 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 59 val sqIdx = new SqPtr 60 val lqIdx = new LqPtr 61 val numLsElem = NumLsElem() 62 } 63 64 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 65 val robIdx = new RobPtr 66 val resp = RespType() 67 val fuType = FuType() 68 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 69 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 70 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 71 } 72 73 object RespType { 74 def apply() = UInt(2.W) 75 76 def isBlocked(resp: UInt) = { 77 resp === block 78 } 79 80 def succeed(resp: UInt) = { 81 resp === success 82 } 83 84 val block = "b00".U 85 val uncertain = "b01".U 86 val success = "b11".U 87 } 88 89 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 90 val status = new Status() 91 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 92 val payload = new DynInst() 93 } 94 95 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 96 val flush = Flipped(ValidIO(new Redirect)) 97 val enq = Flipped(ValidIO(new EntryBundle)) 98 //wakeup 99 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 100 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 101 // vl 102 val vlIsZero = Input(Bool()) 103 val vlIsVlmax = Input(Bool()) 104 //cancel 105 val og0Cancel = Input(ExuOH(backendParams.numExu)) 106 val og1Cancel = Input(ExuOH(backendParams.numExu)) 107 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 108 //deq sel 109 val deqSel = Input(Bool()) 110 val deqPortIdxWrite = Input(UInt(1.W)) 111 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 112 //trans sel 113 val transSel = Input(Bool()) 114 // vector mem only 115 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 116 val sqDeqPtr = Input(new SqPtr) 117 val lqDeqPtr = Input(new LqPtr) 118 }) 119 } 120 121 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 122 //status 123 val valid = Output(Bool()) 124 val canIssue = Output(Bool()) 125 val fuType = Output(FuType()) 126 val robIdx = Output(new RobPtr) 127 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 128 //src 129 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 130 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 131 //deq 132 val isFirstIssue = Output(Bool()) 133 val entry = ValidIO(new EntryBundle) 134 val cancelBypass = Output(Bool()) 135 val deqPortIdxRead = Output(UInt(1.W)) 136 val issueTimerRead = Output(UInt(2.W)) 137 //trans 138 val enqReady = Output(Bool()) 139 val transEntry = ValidIO(new EntryBundle) 140 // debug 141 val entryInValid = Output(Bool()) 142 val entryOutDeqValid = Output(Bool()) 143 val entryOutTransValid = Output(Bool()) 144 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 145 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 146 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 147 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 148 } 149 150 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 151 val validRegNext = Bool() 152 val flushed = Bool() 153 val clear = Bool() 154 val canIssue = Bool() 155 val enqReady = Bool() 156 val deqSuccess = Bool() 157 val srcWakeup = Vec(params.numRegSrc, Bool()) 158 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 159 val vlWakeupByWb = Bool() 160 val srcCancelVec = Vec(params.numRegSrc, Bool()) 161 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 162 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 163 } 164 165 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 166 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 167 common.flushed := status.robIdx.needFlush(commonIn.flush) 168 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 169 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 170 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 171 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 172 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 173 if (params.numRegSrc == 5) { 174 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 175 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 176 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 177 } 178 else 179 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 180 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 181 common.canIssue := validReg && status.canIssue 182 common.enqReady := !validReg || common.clear 183 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 184 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 185 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 186 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 187 srcCancel := srcLoadCancel || ldTransCancel 188 } 189 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 190 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 191 } 192 if(isEnq) { 193 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 194 } else { 195 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 196 } 197 if (params.numRegSrc == 5) { 198 // only when numRegSrc == 5 need vl 199 common.vlWakeupByWb := common.srcWakeupByWB(4) 200 } else { 201 common.vlWakeupByWb := false.B 202 } 203 } 204 205 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 206 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 207 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 208 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 209 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 210 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 211 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 212 val canIssueBypass = Bool() 213 } 214 215 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 216 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 217 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 218 if (params.numRegSrc == 5) { 219 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 220 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 221 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 222 } 223 else 224 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 225 }.toSeq.transpose 226 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 227 228 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 229 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 230 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 231 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 232 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 233 case (exuOH, regExuOH) => 234 exuOH := 0.U.asTypeOf(exuOH) 235 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 236 } 237 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 238 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 239 wakeupVec.asUInt.orR | state 240 }).asUInt.andR 241 } 242 243 244 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 245 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 246 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 247 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 248 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 249 case ((dep, originalDep), deqPortIdx) => 250 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 251 dep := 1.U 252 else 253 dep := originalDep << 1 254 } 255 } 256 } 257 258 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 259 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 260 OH.zip(allExuParams).map{case (oh,e) => 261 if (e.isVfExeUnit) oh else false.B 262 }.reduce(_ || _) 263 } 264 265 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 266 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 267 val cancelByLd = common.srcCancelVec.asUInt.orR 268 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 269 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 270 entryUpdate.status.robIdx := status.robIdx 271 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 272 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 273 val cancel = common.srcCancelVec(srcIdx) 274 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 275 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 276 val wakeup = common.srcWakeup(srcIdx) 277 278 val ignoreOldVd = Wire(Bool()) 279 val vlWakeUpByWb = common.vlWakeupByWb 280 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 281 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 282 val vta = entryReg.payload.vpu.vta 283 val vma = entryReg.payload.vpu.vma 284 val vm = entryReg.payload.vpu.vm 285 val vlIsZero = commonIn.vlIsZero 286 val vlIsVlmax = commonIn.vlIsVlmax 287 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 288 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 289 val srcIsVec = SrcType.isVp(srcStatus.srcType) 290 if (params.numVfSrc > 0 && srcIdx == 2) { 291 /** 292 * the src store the old vd, update it when vl is write back 293 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 294 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 295 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 296 */ 297 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 298 } else { 299 ignoreOldVd := false.B 300 } 301 302 srcStatusNext.psrc := srcStatus.psrc 303 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 304 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 305 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 306 // Vf / Mem -> Vf 307 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 308 MuxCase(srcStatus.dataSources.value, Seq( 309 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 310 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 311 srcStatus.dataSources.readBypass -> DataSource.bypass2, 312 srcStatus.dataSources.readBypass2 -> DataSource.reg, 313 )) 314 } 315 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 316 // Vf / Int -> Mem 317 MuxCase(srcStatus.dataSources.value, Seq( 318 wakeupByIQ -> DataSource.bypass, 319 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 320 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 321 srcStatus.dataSources.readBypass2 -> DataSource.reg, 322 )) 323 } 324 else { 325 MuxCase(srcStatus.dataSources.value, Seq( 326 wakeupByIQ -> DataSource.bypass, 327 srcStatus.dataSources.readBypass -> DataSource.reg, 328 )) 329 }) 330 if(params.hasIQWakeUp) { 331 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 332 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 333 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 334 common.srcLoadDependencyNext(srcIdx)) 335 } else { 336 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 337 } 338 } 339 entryUpdate.status.blocked := false.B 340 entryUpdate.status.issued := MuxCase(status.issued, Seq( 341 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 342 commonIn.deqSel -> true.B, 343 !status.srcReady -> false.B, 344 )) 345 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 346 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 347 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 348 entryUpdate.imm.foreach(_ := entryReg.imm.get) 349 entryUpdate.payload := entryReg.payload 350 if (params.isVecMemIQ) { 351 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 352 } 353 } 354 355 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 356 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 357 commonOut.valid := validReg 358 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 359 else common.canIssue && !common.flushed) 360 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 361 commonOut.robIdx := status.robIdx 362 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 363 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 364 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 365 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 366 dataSourceOut.value := (if (isComp) 367 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 368 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 369 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 370 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 371 )) 372 } else { 373 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 374 wakeupByIQWithoutCancel -> DataSource.forward, 375 )) 376 } 377 else 378 status.srcStatus(srcIdx).dataSources.value) 379 } 380 commonOut.isFirstIssue := !status.firstIssue 381 commonOut.entry.valid := validReg 382 commonOut.entry.bits := entryReg 383 if(isEnq) { 384 commonOut.entry.bits.status := status 385 } 386 commonOut.issueTimerRead := status.issueTimer 387 commonOut.deqPortIdxRead := status.deqPortIdx 388 389 if(params.hasIQWakeUp) { 390 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 391 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 392 if (isComp) 393 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 394 else 395 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 396 } 397 } 398 399 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 400 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 401 if(params.hasIQWakeUp) { 402 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 403 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 404 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 405 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 406 wakeupSrcLoadDependency(srcIdx), 407 status.srcStatus(srcIdx).srcLoadDependency) 408 else status.srcStatus(srcIdx).srcLoadDependency) 409 } 410 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 411 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 412 wakeupSrcLoadDependencyNext(srcIdx), 413 common.srcLoadDependencyNext(srcIdx)) 414 else common.srcLoadDependencyNext(srcIdx)) 415 } 416 } else { 417 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 418 srcLoadDependencyOut := common.srcLoadDependencyNext 419 } 420 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 421 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 422 ldOut := srcLoadDependencyOut(srcIdx) 423 } 424 425 commonOut.enqReady := common.enqReady 426 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 427 commonOut.transEntry.bits := entryUpdate 428 // debug 429 commonOut.entryInValid := commonIn.enq.valid 430 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 431 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 432 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 433 if (params.hasIQWakeUp) { 434 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 435 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 436 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 437 } 438 // vecMem 439 if (params.isVecMemIQ) { 440 commonOut.uopIdx.get := entryReg.payload.uopIdx 441 } 442 } 443 444 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 445 val fromLsq = commonIn.fromLsq.get 446 val vecMemStatus = entryReg.status.vecMem.get 447 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 448 vecMemStatusUpdate := vecMemStatus 449 450 // update blocked 451 entryUpdate.status.blocked := false.B 452 } 453 454 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 455 val origExuOH = Wire(chiselTypeOf(exuOH)) 456 when(wakeupByIQOH.asUInt.orR) { 457 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 458 }.otherwise { 459 origExuOH := regSrcExuOH 460 } 461 exuOH := 0.U.asTypeOf(exuOH) 462 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 463 } 464 465 object IQFuType { 466 def num = FuType.num 467 468 def apply() = Vec(num, Bool()) 469 470 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 471 val res = WireDefault(0.U.asTypeOf(fuType)) 472 fus.foreach(x => res(x.id) := fuType(x.id)) 473 res 474 } 475 } 476 477 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 478 //wakeup 479 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 480 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 481 //cancel 482 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 483 val og0Cancel = Input(ExuOH(backendParams.numExu)) 484 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 485 } 486 487 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 488 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 489 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 490 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 491 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 492 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 493 } 494 495 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 496 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 497 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 498 if (i == 3) 499 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 500 else if (i == 4) 501 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 502 else 503 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 504 }.reduce(_ || _) 505 } 506 507 if (params.hasIQWakeUp) { 508 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 509 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 510 if (params.numRegSrc == 5) { 511 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 512 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 513 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 514 } 515 else 516 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 517 }.toIndexedSeq.transpose 518 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 519 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 520 } else { 521 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 522 } 523 524 if (params.hasIQWakeUp) { 525 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 526 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 527 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 528 } 529 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 530 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 531 } 532 } else { 533 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 534 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 535 } 536 537 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 538 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 539 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 540 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 541 dp := 1.U << (delay - 1) 542 else 543 dp := ldp << delay 544 } 545 } 546 } 547} 548