1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.MathUtils 7import utility.{HasCircularQueuePtrHelper, XSError} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 54 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 val numLsElem = NumLsElem() 61 } 62 63 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 64 val robIdx = new RobPtr 65 val resp = RespType() 66 val fuType = FuType() 67 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 68 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 69 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 70 } 71 72 object RespType { 73 def apply() = UInt(2.W) 74 75 def isBlocked(resp: UInt) = { 76 resp === block 77 } 78 79 def succeed(resp: UInt) = { 80 resp === success 81 } 82 83 val block = "b00".U 84 val uncertain = "b01".U 85 val success = "b11".U 86 } 87 88 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 89 val status = new Status() 90 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 91 val payload = new DynInst() 92 } 93 94 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 95 val flush = Flipped(ValidIO(new Redirect)) 96 val enq = Flipped(ValidIO(new EntryBundle)) 97 //wakeup 98 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 99 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 100 // vl 101 val vlIsZero = Input(Bool()) 102 val vlIsVlmax = Input(Bool()) 103 //cancel 104 val og0Cancel = Input(ExuOH(backendParams.numExu)) 105 val og1Cancel = Input(ExuOH(backendParams.numExu)) 106 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 107 //deq sel 108 val deqSel = Input(Bool()) 109 val deqPortIdxWrite = Input(UInt(1.W)) 110 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 111 //trans sel 112 val transSel = Input(Bool()) 113 // vector mem only 114 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 115 val sqDeqPtr = Input(new SqPtr) 116 val lqDeqPtr = Input(new LqPtr) 117 }) 118 } 119 120 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 121 //status 122 val valid = Output(Bool()) 123 val canIssue = Output(Bool()) 124 val fuType = Output(FuType()) 125 val robIdx = Output(new RobPtr) 126 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 127 //src 128 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 129 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 130 //deq 131 val isFirstIssue = Output(Bool()) 132 val entry = ValidIO(new EntryBundle) 133 val cancelBypass = Output(Bool()) 134 val deqPortIdxRead = Output(UInt(1.W)) 135 val issueTimerRead = Output(UInt(2.W)) 136 //trans 137 val enqReady = Output(Bool()) 138 val transEntry = ValidIO(new EntryBundle) 139 // debug 140 val entryInValid = Output(Bool()) 141 val entryOutDeqValid = Output(Bool()) 142 val entryOutTransValid = Output(Bool()) 143 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 144 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 145 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 146 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 147 } 148 149 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 150 val validRegNext = Bool() 151 val flushed = Bool() 152 val clear = Bool() 153 val canIssue = Bool() 154 val enqReady = Bool() 155 val deqSuccess = Bool() 156 val srcWakeup = Vec(params.numRegSrc, Bool()) 157 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 158 val vlWakeupByWb = Bool() 159 val srcCancelVec = Vec(params.numRegSrc, Bool()) 160 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 161 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 162 } 163 164 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 165 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 166 common.flushed := status.robIdx.needFlush(commonIn.flush) 167 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 168 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 169 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 170 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 171 if (params.numRegSrc == 5) { 172 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 173 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 174 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 175 } 176 else 177 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 178 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 179 common.canIssue := validReg && status.canIssue 180 common.enqReady := !validReg || common.clear 181 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 182 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 183 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 184 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 185 srcCancel := srcLoadCancel || ldTransCancel 186 } 187 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 188 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 189 } 190 if(isEnq) { 191 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 192 } else { 193 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 194 } 195 if (params.numRegSrc == 5) { 196 // only when numRegSrc == 5 need vl 197 common.vlWakeupByWb := common.srcWakeupByWB(4) 198 } else { 199 common.vlWakeupByWb := false.B 200 } 201 } 202 203 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 204 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 205 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 206 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 207 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 208 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 209 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 210 val canIssueBypass = Bool() 211 } 212 213 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 214 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 215 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 216 if (params.numRegSrc == 5) { 217 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 218 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 219 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 220 } 221 else 222 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 223 }.toSeq.transpose 224 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 225 226 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 227 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 228 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 229 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 230 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 231 case (exuOH, regExuOH) => 232 exuOH := 0.U.asTypeOf(exuOH) 233 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 234 } 235 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 236 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 237 wakeupVec.asUInt.orR | state 238 }).asUInt.andR 239 } 240 241 242 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 243 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 244 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 245 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 246 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 247 case ((dep, originalDep), deqPortIdx) => 248 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 249 dep := 1.U 250 else 251 dep := originalDep << 1 252 } 253 } 254 } 255 256 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 257 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 258 OH.zip(allExuParams).map{case (oh,e) => 259 if (e.isVfExeUnit) oh else false.B 260 }.reduce(_ || _) 261 } 262 263 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 264 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 265 val cancelByLd = common.srcCancelVec.asUInt.orR 266 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 267 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 268 entryUpdate.status.robIdx := status.robIdx 269 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 270 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 271 val cancel = common.srcCancelVec(srcIdx) 272 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 273 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 274 val wakeup = common.srcWakeup(srcIdx) 275 276 val ignoreOldVd = Wire(Bool()) 277 val vlWakeUpByWb = common.vlWakeupByWb 278 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 279 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 280 val vta = entryReg.payload.vpu.vta 281 val vma = entryReg.payload.vpu.vma 282 val vm = entryReg.payload.vpu.vm 283 val vlIsZero = commonIn.vlIsZero 284 val vlIsVlmax = commonIn.vlIsVlmax 285 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 286 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 287 val srcIsVec = SrcType.isVp(srcStatus.srcType) 288 if (params.numVfSrc > 0 && srcIdx == 2) { 289 /** 290 * the src store the old vd, update it when vl is write back 291 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 292 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 293 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 294 */ 295 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 296 } else { 297 ignoreOldVd := false.B 298 } 299 300 srcStatusNext.psrc := srcStatus.psrc 301 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 302 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 303 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 304 // Vf / Mem -> Vf 305 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 306 MuxCase(srcStatus.dataSources.value, Seq( 307 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 308 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 309 srcStatus.dataSources.readBypass -> DataSource.bypass2, 310 srcStatus.dataSources.readBypass2 -> DataSource.reg, 311 )) 312 } 313 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 314 // Vf / Int -> Mem 315 MuxCase(srcStatus.dataSources.value, Seq( 316 wakeupByIQ -> DataSource.bypass, 317 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 318 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 319 srcStatus.dataSources.readBypass2 -> DataSource.reg, 320 )) 321 } 322 else { 323 MuxCase(srcStatus.dataSources.value, Seq( 324 wakeupByIQ -> DataSource.bypass, 325 srcStatus.dataSources.readBypass -> DataSource.reg, 326 )) 327 }) 328 if(params.hasIQWakeUp) { 329 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 330 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 331 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 332 common.srcLoadDependencyNext(srcIdx)) 333 } else { 334 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 335 } 336 } 337 entryUpdate.status.blocked := false.B 338 entryUpdate.status.issued := MuxCase(status.issued, Seq( 339 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 340 commonIn.deqSel -> true.B, 341 !status.srcReady -> false.B, 342 )) 343 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 344 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 345 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 346 entryUpdate.imm.foreach(_ := entryReg.imm.get) 347 entryUpdate.payload := entryReg.payload 348 if (params.isVecMemIQ) { 349 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 350 } 351 } 352 353 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 354 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 355 commonOut.valid := validReg 356 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 357 else common.canIssue && !common.flushed) 358 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 359 commonOut.robIdx := status.robIdx 360 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 361 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 362 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 363 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 364 dataSourceOut.value := (if (isComp) 365 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 366 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 367 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 368 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 369 )) 370 } else { 371 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 372 wakeupByIQWithoutCancel -> DataSource.forward, 373 )) 374 } 375 else 376 status.srcStatus(srcIdx).dataSources.value) 377 } 378 commonOut.isFirstIssue := !status.firstIssue 379 commonOut.entry.valid := validReg 380 commonOut.entry.bits := entryReg 381 if(isEnq) { 382 commonOut.entry.bits.status := status 383 } 384 commonOut.issueTimerRead := status.issueTimer 385 commonOut.deqPortIdxRead := status.deqPortIdx 386 387 if(params.hasIQWakeUp) { 388 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 389 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 390 if (isComp) 391 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 392 else 393 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 394 } 395 } 396 397 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 398 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 399 if(params.hasIQWakeUp) { 400 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 401 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 402 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 403 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 404 wakeupSrcLoadDependency(srcIdx), 405 status.srcStatus(srcIdx).srcLoadDependency) 406 else status.srcStatus(srcIdx).srcLoadDependency) 407 } 408 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 409 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 410 wakeupSrcLoadDependencyNext(srcIdx), 411 common.srcLoadDependencyNext(srcIdx)) 412 else common.srcLoadDependencyNext(srcIdx)) 413 } 414 } else { 415 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 416 srcLoadDependencyOut := common.srcLoadDependencyNext 417 } 418 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 419 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 420 ldOut := srcLoadDependencyOut(srcIdx) 421 } 422 423 commonOut.enqReady := common.enqReady 424 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 425 commonOut.transEntry.bits := entryUpdate 426 // debug 427 commonOut.entryInValid := commonIn.enq.valid 428 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 429 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 430 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 431 if (params.hasIQWakeUp) { 432 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 433 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 434 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 435 } 436 // vecMem 437 if (params.isVecMemIQ) { 438 commonOut.uopIdx.get := entryReg.payload.uopIdx 439 } 440 } 441 442 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 443 val fromLsq = commonIn.fromLsq.get 444 val vecMemStatus = entryReg.status.vecMem.get 445 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 446 vecMemStatusUpdate := vecMemStatus 447 448 // update blocked 449 entryUpdate.status.blocked := false.B 450 } 451 452 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 453 val origExuOH = 0.U.asTypeOf(exuOH) 454 when(wakeupByIQOH.asUInt.orR) { 455 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 456 }.otherwise { 457 origExuOH := regSrcExuOH 458 } 459 exuOH := 0.U.asTypeOf(exuOH) 460 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 461 } 462 463 object IQFuType { 464 def num = FuType.num 465 466 def apply() = Vec(num, Bool()) 467 468 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 469 val res = 0.U.asTypeOf(fuType) 470 fus.foreach(x => res(x.id) := fuType(x.id)) 471 res 472 } 473 } 474 475 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 476 //wakeup 477 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 478 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 479 //cancel 480 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 481 val og0Cancel = Input(ExuOH(backendParams.numExu)) 482 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 483 } 484 485 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 486 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 487 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 488 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 489 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 490 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 491 } 492 493 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 494 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 495 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 496 if (i == 3) 497 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 498 else if (i == 4) 499 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 500 else 501 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 502 }.reduce(_ || _) 503 } 504 505 if (params.hasIQWakeUp) { 506 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 507 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 508 if (params.numRegSrc == 5) { 509 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 510 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 511 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 512 } 513 else 514 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 515 }.toIndexedSeq.transpose 516 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 517 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 518 } else { 519 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 520 } 521 522 if (params.hasIQWakeUp) { 523 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 524 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 525 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 526 } 527 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 528 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 529 } 530 } else { 531 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 532 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 533 } 534 535 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 536 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 537 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 538 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 539 dp := 1.U << (delay - 1) 540 else 541 dp := ldp << delay 542 } 543 } 544 } 545} 546