1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, SqPtr} 16import xiangshan.mem.Bundles.MemWaitUpdateReqBundle 17 18object EntryBundles extends HasCircularQueuePtrHelper { 19 20 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 21 //basic status 22 val robIdx = new RobPtr 23 val fuType = IQFuType() 24 //src status 25 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 26 //issue status 27 val blocked = Bool() 28 val issued = Bool() 29 val firstIssue = Bool() 30 val issueTimer = UInt(2.W) 31 val deqPortIdx = UInt(1.W) 32 //vector mem status 33 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 34 35 def srcReady: Bool = { 36 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 37 } 38 39 def canIssue: Bool = { 40 srcReady && !issued && !blocked 41 } 42 43 def mergedLoadDependency: Vec[UInt] = { 44 srcStatus.map(_.srcLoadDependency).reduce({ 45 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 46 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 47 } 48 } 49 50 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 51 val psrc = UInt(params.rdPregIdxWidth.W) 52 val srcType = SrcType() 53 val srcState = SrcState() 54 val dataSources = DataSource() 55 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 56 val exuSources = Option.when(params.hasIQWakeUp)(ExuSource()) 57 //reg cache 58 val useRegCache = Option.when(params.needReadRegCache)(Bool()) 59 val regCacheIdx = Option.when(params.needReadRegCache)(UInt(RegCacheIdxWidth.W)) 60 } 61 62 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 63 val sqIdx = new SqPtr 64 val lqIdx = new LqPtr 65 val numLsElem = NumLsElem() 66 } 67 68 class EntryDeqRespBundle(implicit p: Parameters, val params: IssueBlockParams) extends XSBundle { 69 val robIdx = new RobPtr 70 val resp = RespType() 71 val fuType = FuType() 72 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 73 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 74 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 75 } 76 77 object RespType { 78 def apply() = UInt(2.W) 79 80 def isBlocked(resp: UInt) = { 81 resp === block 82 } 83 84 def succeed(resp: UInt) = { 85 resp === success 86 } 87 88 val block = "b00".U 89 val uncertain = "b01".U 90 val success = "b11".U 91 } 92 93 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 94 val status = new Status() 95 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 96 val payload = new DynInst() 97 } 98 99 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 100 val flush = Flipped(ValidIO(new Redirect)) 101 val enq = Flipped(ValidIO(new EntryBundle)) 102 //wakeup 103 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 104 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 105 // vl 106 val vlFromIntIsZero = Input(Bool()) 107 val vlFromIntIsVlmax = Input(Bool()) 108 val vlFromVfIsZero = Input(Bool()) 109 val vlFromVfIsVlmax = Input(Bool()) 110 //cancel 111 val og0Cancel = Input(ExuVec()) 112 val og1Cancel = Input(ExuVec()) 113 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 114 //deq sel 115 val deqSel = Input(Bool()) 116 val deqPortIdxWrite = Input(UInt(1.W)) 117 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 118 //trans sel 119 val transSel = Input(Bool()) 120 // vector mem only 121 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 122 val sqDeqPtr = Input(new SqPtr) 123 val lqDeqPtr = Input(new LqPtr) 124 }) 125 } 126 127 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 128 //status 129 val valid = Output(Bool()) 130 val issued = Output(Bool()) 131 val canIssue = Output(Bool()) 132 val fuType = Output(FuType()) 133 val robIdx = Output(new RobPtr) 134 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 135 //src 136 val dataSources = Vec(params.numRegSrc, Output(DataSource())) 137 val exuSources = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuSource()))) 138 //deq 139 val isFirstIssue = Output(Bool()) 140 val entry = ValidIO(new EntryBundle) 141 val cancelBypass = Output(Bool()) 142 val deqPortIdxRead = Output(UInt(1.W)) 143 val issueTimerRead = Output(UInt(2.W)) 144 //trans 145 val enqReady = Output(Bool()) 146 val transEntry = ValidIO(new EntryBundle) 147 // debug 148 val entryInValid = Output(Bool()) 149 val entryOutDeqValid = Output(Bool()) 150 val entryOutTransValid = Output(Bool()) 151 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 152 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 153 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 154 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 155 } 156 157 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 158 val validRegNext = Bool() 159 val flushed = Bool() 160 val clear = Bool() 161 val canIssue = Bool() 162 val enqReady = Bool() 163 val deqSuccess = Bool() 164 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 165 val vlWakeupByIntWb = Bool() 166 val vlWakeupByVfWb = Bool() 167 val srcCancelVec = Vec(params.numRegSrc, Bool()) 168 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 169 val srcLoadTransCancelVec = Vec(params.numRegSrc, Bool()) 170 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 171 } 172 173 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 174 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 175 common.flushed := status.robIdx.needFlush(commonIn.flush) 176 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 177 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 178 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 179 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 180 if (params.numRegSrc == 5) { 181 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 182 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 183 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 184 } 185 else 186 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 187 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 188 common.canIssue := validReg && status.canIssue 189 common.enqReady := !validReg || commonIn.transSel 190 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 191 common.srcCancelVec.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case ((srcCancel, wakeUpByIQVec), srcIdx) => 192 common.srcLoadTransCancelVec(srcIdx) := (if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B) 193 common.srcLoadCancelVec(srcIdx) := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 194 srcCancel := common.srcLoadTransCancelVec(srcIdx) || common.srcLoadCancelVec(srcIdx) 195 } 196 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 197 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 198 } 199 if(isEnq) { 200 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 201 } else { 202 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 203 } 204 if (params.numRegSrc == 5) { 205 // only when numRegSrc == 5 need vl 206 val wakeUpFromVl = VecInit(commonIn.wakeUpFromWB.map{ bundle => 207 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 208 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 209 }) 210 var numVecWb = params.backendParam.getVfWBExeGroup.size 211 var numV0Wb = params.backendParam.getV0WBExeGroup.size 212 var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort 213 var vfSchdVlWbPort = p(XSCoreParamsKey).vfSchdVlWbPort 214 // int wb is first bit of vlwb, which is after vfwb and v0wb 215 common.vlWakeupByIntWb := wakeUpFromVl(numVecWb + numV0Wb + intSchdVlWbPort) 216 // vf wb is second bit of wb 217 common.vlWakeupByVfWb := wakeUpFromVl(numVecWb + numV0Wb + vfSchdVlWbPort) 218 } else { 219 common.vlWakeupByIntWb := false.B 220 common.vlWakeupByVfWb := false.B 221 } 222 } 223 224 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 225 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 226 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 227 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 228 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 229 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 230 val canIssueBypass = Bool() 231 } 232 233 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 234 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 235 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 236 if (params.numRegSrc == 5) { 237 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 238 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 239 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 240 } 241 else 242 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 243 }.toSeq.transpose 244 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 245 246 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 247 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 248 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 249 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 250 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 251 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 252 wakeupVec.asUInt.orR | state 253 }).asUInt.andR 254 } 255 256 257 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 258 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 259 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 260 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 261 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 262 case ((dep, originalDep), deqPortIdx) => 263 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 264 dep := 1.U 265 else 266 dep := originalDep << 1 267 } 268 } 269 } 270 271 def wakeUpByVf(exuSource: ExuSource)(implicit p: Parameters, params: IssueBlockParams): Bool = { 272 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 273 exuSource.toExuOH(params).zip(allExuParams).map{case (oh,e) => 274 if (e.isVfExeUnit) oh else false.B 275 }.reduce(_ || _) 276 } 277 278 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 279 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 280 val cancelBypassVec = Wire(Vec(params.numRegSrc, Bool())) 281 val srcCancelByLoad = common.srcLoadCancelVec.asUInt.orR 282 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 283 entryUpdate.status.robIdx := status.robIdx 284 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 285 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 286 val srcLoadCancel = common.srcLoadCancelVec(srcIdx) 287 val loadTransCancel = common.srcLoadTransCancelVec(srcIdx) 288 val wakeupByWB = common.srcWakeupByWB(srcIdx) 289 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR && !loadTransCancel 290 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 291 val wakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 292 cancelBypassVec(srcIdx) := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, loadTransCancel, srcLoadCancel) 293 else srcLoadCancel) 294 295 val ignoreOldVd = Wire(Bool()) 296 val vlWakeUpByIntWb = common.vlWakeupByIntWb 297 val vlWakeUpByVfWb = common.vlWakeupByVfWb 298 val isDependOldVd = entryReg.payload.vpu.isDependOldVd 299 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 300 val vta = entryReg.payload.vpu.vta 301 val vma = entryReg.payload.vpu.vma 302 val vm = entryReg.payload.vpu.vm 303 val vlFromIntIsZero = commonIn.vlFromIntIsZero 304 val vlFromIntIsVlmax = commonIn.vlFromIntIsVlmax 305 val vlFromVfIsZero = commonIn.vlFromVfIsZero 306 val vlFromVfIsVlmax = commonIn.vlFromVfIsVlmax 307 val vlIsVlmax = (vlFromIntIsVlmax && vlWakeUpByIntWb) || (vlFromVfIsVlmax && vlWakeUpByVfWb) 308 val vlIsNonZero = (!vlFromIntIsZero && vlWakeUpByIntWb) || (!vlFromVfIsZero && vlWakeUpByVfWb) 309 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 310 val ignoreWhole = (vm =/= 0.U || vma) && vta 311 val srcIsVec = SrcType.isVp(srcStatus.srcType) 312 if (params.numVfSrc > 0 && srcIdx == 2) { 313 /** 314 * the src store the old vd, update it when vl is write back 315 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 316 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 317 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 318 */ 319 ignoreOldVd := srcIsVec && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole) 320 } else { 321 ignoreOldVd := false.B 322 } 323 324 srcStatusNext.psrc := srcStatus.psrc 325 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 326 srcStatusNext.srcState := srcStatus.srcState & !srcLoadCancel | wakeupByWB | wakeupByIQ | ignoreOldVd 327 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 328 // Vf / Mem -> Vf 329 MuxCase(srcStatus.dataSources.value, Seq( 330 ignoreOldVd -> DataSource.imm, 331 (wakeupByIQ && wakeupByMemIQ) -> DataSource.bypass2, 332 (wakeupByIQ && !wakeupByMemIQ) -> DataSource.bypass, 333 srcStatus.dataSources.readBypass -> DataSource.bypass2, 334 srcStatus.dataSources.readBypass2 -> DataSource.reg, 335 )) 336 } 337 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 338 // Vf / Int -> Mem 339 MuxCase(srcStatus.dataSources.value, Seq( 340 wakeupByIQ -> DataSource.bypass, 341 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.exuSources.get)) -> DataSource.bypass2, 342 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.exuSources.get)) -> DataSource.reg, 343 srcStatus.dataSources.readBypass2 -> DataSource.reg, 344 )) 345 } 346 else { 347 MuxCase(srcStatus.dataSources.value, Seq( 348 ignoreOldVd -> DataSource.imm, 349 wakeupByIQ -> DataSource.bypass, 350 srcStatus.dataSources.readBypass -> DataSource.reg, 351 )) 352 }) 353 if(params.hasIQWakeUp) { 354 srcStatusNext.exuSources.get.value := Mux(wakeupByIQOH.asUInt.orR, 355 ExuSource().fromExuOH(params, Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)))), 356 srcStatus.exuSources.get.value) 357 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 358 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 359 common.srcLoadDependencyNext(srcIdx)) 360 } else { 361 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 362 } 363 364 if (params.needReadRegCache) { 365 val wakeupSrcExuWriteRC = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.needWriteRegCache) 366 val wakeupRC = wakeupSrcExuWriteRC.map(_._1).fold(false.B)(_ || _) && SrcType.isXp(srcStatus.srcType) 367 val wakeupRCIdx = Mux1H(wakeupSrcExuWriteRC.map(_._1), wakeupSrcExuWriteRC.map(_._2.bits.rcDest.get)) 368 val replaceRC = wakeupSrcExuWriteRC.map(x => x._2.bits.rfWen && x._2.bits.rcDest.get === srcStatus.regCacheIdx.get).fold(false.B)(_ || _) 369 370 srcStatusNext.useRegCache.get := srcStatus.useRegCache.get && !(srcLoadCancel || replaceRC) || wakeupRC 371 srcStatusNext.regCacheIdx.get := Mux(wakeupRC, wakeupRCIdx, srcStatus.regCacheIdx.get) 372 } 373 } 374 entryUpdate.status.blocked := false.B 375 entryUpdate.status.issued := MuxCase(status.issued, Seq( 376 (commonIn.deqSel && !cancelBypassVec.asUInt.orR) -> true.B, 377 (srcCancelByLoad || respIssueFail) -> false.B, 378 )) 379 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 380 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 381 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 382 entryUpdate.imm.foreach(_ := entryReg.imm.get) 383 entryUpdate.payload := entryReg.payload 384 if (params.isVecMemIQ) { 385 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 386 } 387 } 388 389 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 390 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 391 commonOut.valid := validReg 392 commonOut.issued := entryReg.status.issued 393 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 394 else common.canIssue && !common.flushed) 395 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 396 commonOut.robIdx := status.robIdx 397 commonOut.dataSources.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 398 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 399 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 400 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 401 val useRegCache = status.srcStatus(srcIdx).useRegCache.getOrElse(false.B) && status.srcStatus(srcIdx).dataSources.readReg 402 dataSourceOut.value := (if (isComp) 403 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 404 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 405 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 406 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 407 )) 408 } else { 409 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 410 wakeupByIQWithoutCancel -> DataSource.forward, 411 useRegCache -> DataSource.regcache, 412 )) 413 } 414 else { 415 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 416 useRegCache -> DataSource.regcache, 417 )) 418 }) 419 } 420 commonOut.isFirstIssue := !status.firstIssue 421 commonOut.entry.valid := validReg 422 commonOut.entry.bits := entryReg 423 if(isEnq) { 424 commonOut.entry.bits.status := status 425 } 426 commonOut.issueTimerRead := status.issueTimer 427 commonOut.deqPortIdxRead := status.deqPortIdx 428 429 if(params.hasIQWakeUp) { 430 commonOut.exuSources.get.zipWithIndex.foreach{ case (exuSourceOut, srcIdx) => 431 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 432 if (isComp) 433 exuSourceOut.value := Mux(wakeupByIQWithoutCancelOH.asUInt.orR, 434 ExuSource().fromExuOH(params, Mux1H(wakeupByIQWithoutCancelOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)))), 435 status.srcStatus(srcIdx).exuSources.get.value) 436 else 437 exuSourceOut.value := status.srcStatus(srcIdx).exuSources.get.value 438 } 439 } 440 441 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 442 if(params.hasIQWakeUp) { 443 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 444 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 445 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 446 wakeupSrcLoadDependencyNext(srcIdx), 447 common.srcLoadDependencyNext(srcIdx)) 448 else common.srcLoadDependencyNext(srcIdx)) 449 } 450 } else { 451 srcLoadDependencyOut := common.srcLoadDependencyNext 452 } 453 commonOut.cancelBypass := VecInit(hasIQWakeupGet.srcWakeupByIQWithoutCancel.zipWithIndex.map{ case (wakeupVec, srcIdx) => 454 if (isComp) Mux(wakeupVec.asUInt.orR, common.srcLoadTransCancelVec(srcIdx), common.srcLoadCancelVec(srcIdx)) 455 else common.srcLoadCancelVec(srcIdx) 456 }).asUInt.orR 457 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 458 ldOut := srcLoadDependencyOut(srcIdx) 459 } 460 461 commonOut.enqReady := common.enqReady 462 commonOut.transEntry.valid := validReg && !common.flushed && !status.issued 463 commonOut.transEntry.bits := entryUpdate 464 // debug 465 commonOut.entryInValid := commonIn.enq.valid 466 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 467 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 468 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 469 if (params.hasIQWakeUp) { 470 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 471 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 472 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 473 } 474 // vecMem 475 if (params.isVecMemIQ) { 476 commonOut.uopIdx.get := entryReg.payload.uopIdx 477 } 478 } 479 480 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 481 val fromLsq = commonIn.fromLsq.get 482 val vecMemStatus = entryReg.status.vecMem.get 483 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 484 vecMemStatusUpdate := vecMemStatus 485 486 val isFirstLoad = entryReg.status.vecMem.get.lqIdx === fromLsq.lqDeqPtr 487 488 val isVleff = entryReg.payload.vpu.isVleff 489 // update blocked 490 entryUpdate.status.blocked := !isFirstLoad && isVleff 491 } 492 493 object IQFuType { 494 def num = FuType.num 495 496 def apply() = Vec(num, Bool()) 497 498 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 499 val res = WireDefault(0.U.asTypeOf(fuType)) 500 fus.foreach(x => res(x.id) := fuType(x.id)) 501 res 502 } 503 } 504 505 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 506 //wakeup 507 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 508 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 509 //cancel 510 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 511 val og0Cancel = Input(ExuVec()) 512 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 513 } 514 515 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 516 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 517 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 518 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 519 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 520 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 521 } 522 523 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 524 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 525 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 526 if (i == 3) 527 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 528 else if (i == 4) 529 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 530 else 531 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 532 }.reduce(_ || _) 533 } 534 535 if (params.hasIQWakeUp) { 536 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 537 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 538 if (params.numRegSrc == 5) { 539 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 540 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 541 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 542 } 543 else 544 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 545 }.toIndexedSeq.transpose 546 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 547 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 548 } else { 549 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 550 } 551 552 if (params.hasIQWakeUp) { 553 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 554 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 555 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 556 } 557 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 558 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 559 } 560 } else { 561 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 562 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 563 } 564 565 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 566 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 567 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 568 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 569 dp := 1.U << (delay - 1) 570 else 571 dp := ldp << delay 572 } 573 } 574 } 575} 576