1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper, XSError} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 54 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 val numLsElem = NumLsElem() 61 } 62 63 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 64 val robIdx = new RobPtr 65 val resp = RespType() 66 val fuType = FuType() 67 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 68 } 69 70 object RespType { 71 def apply() = UInt(2.W) 72 73 def isBlocked(resp: UInt) = { 74 resp === block 75 } 76 77 def succeed(resp: UInt) = { 78 resp === success 79 } 80 81 val block = "b00".U 82 val uncertain = "b01".U 83 val success = "b11".U 84 } 85 86 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 87 val status = new Status() 88 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 89 val payload = new DynInst() 90 } 91 92 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val flush = Flipped(ValidIO(new Redirect)) 94 val enq = Flipped(ValidIO(new EntryBundle)) 95 //wakeup 96 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 97 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 98 // vl 99 val vlIsZero = Input(Bool()) 100 val vlIsVlmax = Input(Bool()) 101 //cancel 102 val og0Cancel = Input(ExuOH(backendParams.numExu)) 103 val og1Cancel = Input(ExuOH(backendParams.numExu)) 104 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 105 //deq sel 106 val deqSel = Input(Bool()) 107 val deqPortIdxWrite = Input(UInt(1.W)) 108 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 109 //trans sel 110 val transSel = Input(Bool()) 111 // vector mem only 112 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 113 val sqDeqPtr = Input(new SqPtr) 114 val lqDeqPtr = Input(new LqPtr) 115 }) 116 } 117 118 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 119 //status 120 val valid = Output(Bool()) 121 val canIssue = Output(Bool()) 122 val fuType = Output(FuType()) 123 val robIdx = Output(new RobPtr) 124 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 125 //src 126 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 127 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val cancelBypass = Output(Bool()) 132 val deqPortIdxRead = Output(UInt(1.W)) 133 val issueTimerRead = Output(UInt(2.W)) 134 //trans 135 val enqReady = Output(Bool()) 136 val transEntry = ValidIO(new EntryBundle) 137 // debug 138 val entryInValid = Output(Bool()) 139 val entryOutDeqValid = Output(Bool()) 140 val entryOutTransValid = Output(Bool()) 141 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 142 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 143 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 144 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 145 } 146 147 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 148 val validRegNext = Bool() 149 val flushed = Bool() 150 val clear = Bool() 151 val canIssue = Bool() 152 val enqReady = Bool() 153 val deqSuccess = Bool() 154 val srcWakeup = Vec(params.numRegSrc, Bool()) 155 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 156 val vlWakeupByWb = Bool() 157 val srcCancelVec = Vec(params.numRegSrc, Bool()) 158 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 159 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 160 } 161 162 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 163 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 164 common.flushed := status.robIdx.needFlush(commonIn.flush) 165 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 166 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 167 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 168 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 169 if (params.numRegSrc == 5) { 170 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 171 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 172 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 173 } 174 else 175 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 176 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 177 common.canIssue := validReg && status.canIssue 178 common.enqReady := !validReg || common.clear 179 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 180 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 181 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 182 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 183 srcCancel := srcLoadCancel || ldTransCancel 184 } 185 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 186 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 187 } 188 if(isEnq) { 189 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 190 } else { 191 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 192 } 193 if (params.numRegSrc == 5) { 194 // only when numRegSrc == 5 need vl 195 common.vlWakeupByWb := common.srcWakeupByWB(4) 196 } else { 197 common.vlWakeupByWb := false.B 198 } 199 } 200 201 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 202 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 203 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 204 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 205 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 206 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 207 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 208 val canIssueBypass = Bool() 209 } 210 211 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 212 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 213 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 214 if (params.numRegSrc == 5) { 215 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 216 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 217 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 218 } 219 else 220 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 221 }.toSeq.transpose 222 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 223 224 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 225 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 226 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 227 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 228 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 229 case (exuOH, regExuOH) => 230 exuOH := 0.U.asTypeOf(exuOH) 231 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 232 } 233 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 234 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 235 wakeupVec.asUInt.orR | state 236 }).asUInt.andR 237 } 238 239 240 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 241 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 242 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 243 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 244 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 245 case ((dep, originalDep), deqPortIdx) => 246 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 247 dep := 1.U 248 else 249 dep := originalDep << 1 250 } 251 } 252 } 253 254 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 255 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 256 OH.zip(allExuParams).map{case (oh,e) => 257 if (e.isVfExeUnit) oh else false.B 258 }.reduce(_ || _) 259 } 260 261 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 262 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 263 val cancelByLd = common.srcCancelVec.asUInt.orR 264 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 265 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 266 entryUpdate.status.robIdx := status.robIdx 267 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 268 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 269 val cancel = common.srcCancelVec(srcIdx) 270 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 271 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 272 val wakeup = common.srcWakeup(srcIdx) 273 274 val ignoreOldVd = Wire(Bool()) 275 val vlWakeUpByWb = common.vlWakeupByWb 276 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 277 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 278 val vta = entryReg.payload.vpu.vta 279 val vma = entryReg.payload.vpu.vma 280 val vm = entryReg.payload.vpu.vm 281 val vlIsZero = commonIn.vlIsZero 282 val vlIsVlmax = commonIn.vlIsVlmax 283 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 284 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 285 val srcIsVec = SrcType.isVp(srcStatus.srcType) 286 if (params.numVfSrc > 0 && srcIdx == 2) { 287 /** 288 * the src store the old vd, update it when vl is write back 289 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 290 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 291 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 292 */ 293 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 294 } else { 295 ignoreOldVd := false.B 296 } 297 298 srcStatusNext.psrc := srcStatus.psrc 299 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 300 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 301 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 302 // Vf / Mem -> Vf 303 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 304 MuxCase(srcStatus.dataSources.value, Seq( 305 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 306 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 307 srcStatus.dataSources.readBypass -> DataSource.bypass2, 308 srcStatus.dataSources.readBypass2 -> DataSource.reg, 309 )) 310 } 311 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 312 // Vf / Int -> Mem 313 MuxCase(srcStatus.dataSources.value, Seq( 314 wakeupByIQ -> DataSource.bypass, 315 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 316 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 317 srcStatus.dataSources.readBypass2 -> DataSource.reg, 318 )) 319 } 320 else { 321 MuxCase(srcStatus.dataSources.value, Seq( 322 wakeupByIQ -> DataSource.bypass, 323 srcStatus.dataSources.readBypass -> DataSource.reg, 324 )) 325 }) 326 if(params.hasIQWakeUp) { 327 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 328 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 329 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 330 common.srcLoadDependencyNext(srcIdx)) 331 } else { 332 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 333 } 334 } 335 entryUpdate.status.blocked := false.B 336 entryUpdate.status.issued := MuxCase(status.issued, Seq( 337 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 338 commonIn.deqSel -> true.B, 339 !status.srcReady -> false.B, 340 )) 341 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 342 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 343 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 344 entryUpdate.imm.foreach(_ := entryReg.imm.get) 345 entryUpdate.payload := entryReg.payload 346 if (params.isVecMemIQ) { 347 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 348 } 349 } 350 351 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 352 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 353 commonOut.valid := validReg 354 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 355 else common.canIssue && !common.flushed) 356 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 357 commonOut.robIdx := status.robIdx 358 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 359 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 360 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 361 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 362 dataSourceOut.value := (if (isComp) 363 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 364 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 365 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 366 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 367 )) 368 } else { 369 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 370 wakeupByIQWithoutCancel -> DataSource.forward, 371 )) 372 } 373 else 374 status.srcStatus(srcIdx).dataSources.value) 375 } 376 commonOut.isFirstIssue := !status.firstIssue 377 commonOut.entry.valid := validReg 378 commonOut.entry.bits := entryReg 379 if(isEnq) { 380 commonOut.entry.bits.status := status 381 } 382 commonOut.issueTimerRead := status.issueTimer 383 commonOut.deqPortIdxRead := status.deqPortIdx 384 385 if(params.hasIQWakeUp) { 386 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 387 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 388 if (isComp) 389 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 390 else 391 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 392 } 393 } 394 395 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 396 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 397 if(params.hasIQWakeUp) { 398 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 399 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 400 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 401 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 402 wakeupSrcLoadDependency(srcIdx), 403 status.srcStatus(srcIdx).srcLoadDependency) 404 else status.srcStatus(srcIdx).srcLoadDependency) 405 } 406 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 407 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 408 wakeupSrcLoadDependencyNext(srcIdx), 409 common.srcLoadDependencyNext(srcIdx)) 410 else common.srcLoadDependencyNext(srcIdx)) 411 } 412 } else { 413 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 414 srcLoadDependencyOut := common.srcLoadDependencyNext 415 } 416 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 417 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 418 ldOut := srcLoadDependencyOut(srcIdx) 419 } 420 421 commonOut.enqReady := common.enqReady 422 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 423 commonOut.transEntry.bits := entryUpdate 424 // debug 425 commonOut.entryInValid := commonIn.enq.valid 426 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 427 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 428 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 429 if (params.hasIQWakeUp) { 430 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 431 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 432 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 433 } 434 // vecMem 435 if (params.isVecMemIQ) { 436 commonOut.uopIdx.get := entryReg.payload.uopIdx 437 } 438 } 439 440 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 441 val fromLsq = commonIn.fromLsq.get 442 val vecMemStatus = entryReg.status.vecMem.get 443 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 444 vecMemStatusUpdate := vecMemStatus 445 446 // update blocked 447 entryUpdate.status.blocked := false.B 448 } 449 450 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 451 val origExuOH = 0.U.asTypeOf(exuOH) 452 when(wakeupByIQOH.asUInt.orR) { 453 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 454 }.otherwise { 455 origExuOH := regSrcExuOH 456 } 457 exuOH := 0.U.asTypeOf(exuOH) 458 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 459 } 460 461 object IQFuType { 462 def num = FuType.num 463 464 def apply() = Vec(num, Bool()) 465 466 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 467 val res = 0.U.asTypeOf(fuType) 468 fus.foreach(x => res(x.id) := fuType(x.id)) 469 res 470 } 471 } 472 473 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 474 //wakeup 475 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 476 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 477 //cancel 478 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 479 val og0Cancel = Input(ExuOH(backendParams.numExu)) 480 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 481 } 482 483 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 484 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 485 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 486 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 487 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 488 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 489 } 490 491 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 492 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 493 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 494 if (i == 3) 495 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 496 else if (i == 4) 497 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 498 else 499 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 500 }.reduce(_ || _) 501 } 502 503 if (params.hasIQWakeUp) { 504 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 505 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 506 if (params.numRegSrc == 5) { 507 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 508 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 509 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 510 } 511 else 512 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 513 }.toIndexedSeq.transpose 514 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 515 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 516 } else { 517 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 518 } 519 520 if (params.hasIQWakeUp) { 521 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 522 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 523 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 524 } 525 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 526 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 527 } 528 } else { 529 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 530 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 531 } 532 533 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 534 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 535 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 536 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 537 dp := 1.U << (delay - 1) 538 else 539 dp := ldp << delay 540 } 541 } 542 } 543} 544