1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper, XSError} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 54 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 val numLsElem = NumLsElem() 61 } 62 63 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 64 val robIdx = new RobPtr 65 val resp = RespType() 66 val fuType = FuType() 67 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 68 } 69 70 object RespType { 71 def apply() = UInt(2.W) 72 73 def isBlocked(resp: UInt) = { 74 resp === block 75 } 76 77 def succeed(resp: UInt) = { 78 resp === success 79 } 80 81 val block = "b00".U 82 val uncertain = "b01".U 83 val success = "b11".U 84 } 85 86 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 87 val status = new Status() 88 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 89 val payload = new DynInst() 90 } 91 92 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val flush = Flipped(ValidIO(new Redirect)) 94 val enq = Flipped(ValidIO(new EntryBundle)) 95 //wakeup 96 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 97 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 98 // vl 99 val vlIsZero = Input(Bool()) 100 val vlIsVlmax = Input(Bool()) 101 //cancel 102 val og0Cancel = Input(ExuOH(backendParams.numExu)) 103 val og1Cancel = Input(ExuOH(backendParams.numExu)) 104 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 105 //deq sel 106 val deqSel = Input(Bool()) 107 val deqPortIdxWrite = Input(UInt(1.W)) 108 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 109 //trans sel 110 val transSel = Input(Bool()) 111 // vector mem only 112 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 113 val sqDeqPtr = Input(new SqPtr) 114 val lqDeqPtr = Input(new LqPtr) 115 }) 116 } 117 118 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 119 //status 120 val valid = Output(Bool()) 121 val canIssue = Output(Bool()) 122 val fuType = Output(FuType()) 123 val robIdx = Output(new RobPtr) 124 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 125 //src 126 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 127 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val cancelBypass = Output(Bool()) 132 val deqPortIdxRead = Output(UInt(1.W)) 133 val issueTimerRead = Output(UInt(2.W)) 134 //trans 135 val enqReady = Output(Bool()) 136 val transEntry = ValidIO(new EntryBundle) 137 // debug 138 val entryInValid = Output(Bool()) 139 val entryOutDeqValid = Output(Bool()) 140 val entryOutTransValid = Output(Bool()) 141 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 142 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 143 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 144 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 145 } 146 147 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 148 val validRegNext = Bool() 149 val flushed = Bool() 150 val clear = Bool() 151 val canIssue = Bool() 152 val enqReady = Bool() 153 val deqSuccess = Bool() 154 val srcWakeup = Vec(params.numRegSrc, Bool()) 155 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 156 val vlWakeupByWb = Bool() 157 val srcCancelVec = Vec(params.numRegSrc, Bool()) 158 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 159 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 160 } 161 162 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 163 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 164 common.flushed := status.robIdx.needFlush(commonIn.flush) 165 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 166 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 167 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 168 common.canIssue := validReg && status.canIssue 169 common.enqReady := !validReg || common.clear 170 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 171 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 172 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 173 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 174 srcCancel := srcLoadCancel || ldTransCancel 175 } 176 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 177 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 178 } 179 if(isEnq) { 180 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 181 } else { 182 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 183 } 184 if (params.numRegSrc == 5) { 185 // only when numRegSrc == 5 need vl 186 common.vlWakeupByWb := common.srcWakeupByWB(4) 187 } else { 188 common.vlWakeupByWb := false.B 189 } 190 } 191 192 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 193 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 194 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 195 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 196 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 197 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 198 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 199 val canIssueBypass = Bool() 200 } 201 202 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 203 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 204 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 205 ).toSeq.transpose 206 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 207 208 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 209 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 210 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 211 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 212 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 213 case (exuOH, regExuOH) => 214 exuOH := 0.U.asTypeOf(exuOH) 215 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 216 } 217 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 218 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 219 wakeupVec.asUInt.orR | state 220 }).asUInt.andR 221 } 222 223 224 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 225 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 226 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 227 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 228 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 229 case ((dep, originalDep), deqPortIdx) => 230 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 231 dep := 1.U 232 else 233 dep := originalDep << 1 234 } 235 } 236 } 237 238 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 239 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 240 OH.zip(allExuParams).map{case (oh,e) => 241 if (e.isVfExeUnit) oh else false.B 242 }.reduce(_ || _) 243 } 244 245 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 246 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 247 val cancelByLd = common.srcCancelVec.asUInt.orR 248 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 249 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 250 entryUpdate.status.robIdx := status.robIdx 251 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 252 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 253 val cancel = common.srcCancelVec(srcIdx) 254 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 255 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 256 val wakeup = common.srcWakeup(srcIdx) 257 258 val ignoreOldVd = Wire(Bool()) 259 val vlWakeUpByWb = common.vlWakeupByWb 260 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 261 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 262 val vta = entryReg.payload.vpu.vta 263 val vma = entryReg.payload.vpu.vma 264 val vm = entryReg.payload.vpu.vm 265 val vlIsZero = commonIn.vlIsZero 266 val vlIsVlmax = commonIn.vlIsVlmax 267 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 268 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 269 val srcIsVec = SrcType.isVp(srcStatus.srcType) 270 if (params.numVfSrc > 0 && srcIdx == 2) { 271 /** 272 * the src store the old vd, update it when vl is write back 273 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 274 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 275 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 276 */ 277 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 278 } else { 279 ignoreOldVd := false.B 280 } 281 282 srcStatusNext.psrc := srcStatus.psrc 283 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 284 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 285 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 286 // Vf / Mem -> Vf 287 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 288 MuxCase(srcStatus.dataSources.value, Seq( 289 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 290 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 291 srcStatus.dataSources.readBypass -> DataSource.bypass2, 292 srcStatus.dataSources.readBypass2 -> DataSource.reg, 293 )) 294 } 295 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 296 // Vf / Int -> Mem 297 MuxCase(srcStatus.dataSources.value, Seq( 298 wakeupByIQ -> DataSource.bypass, 299 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 300 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 301 srcStatus.dataSources.readBypass2 -> DataSource.reg, 302 )) 303 } 304 else { 305 MuxCase(srcStatus.dataSources.value, Seq( 306 wakeupByIQ -> DataSource.bypass, 307 srcStatus.dataSources.readBypass -> DataSource.reg, 308 )) 309 }) 310 if(params.hasIQWakeUp) { 311 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 312 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 313 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 314 common.srcLoadDependencyNext(srcIdx)) 315 } else { 316 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 317 } 318 } 319 entryUpdate.status.blocked := false.B 320 entryUpdate.status.issued := MuxCase(status.issued, Seq( 321 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 322 commonIn.deqSel -> true.B, 323 !status.srcReady -> false.B, 324 )) 325 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 326 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b11".U)) 327 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 328 entryUpdate.imm.foreach(_ := entryReg.imm.get) 329 entryUpdate.payload := entryReg.payload 330 if (params.isVecMemIQ) { 331 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 332 } 333 } 334 335 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 336 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 337 commonOut.valid := validReg 338 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 339 else common.canIssue && !common.flushed) 340 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 341 commonOut.robIdx := status.robIdx 342 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 343 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 344 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 345 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 346 dataSourceOut.value := (if (isComp) 347 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 348 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 349 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 350 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 351 )) 352 } else { 353 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 354 wakeupByIQWithoutCancel -> DataSource.forward, 355 )) 356 } 357 else 358 status.srcStatus(srcIdx).dataSources.value) 359 } 360 commonOut.isFirstIssue := !status.firstIssue 361 commonOut.entry.valid := validReg 362 commonOut.entry.bits := entryReg 363 if(isEnq) { 364 commonOut.entry.bits.status := status 365 } 366 commonOut.issueTimerRead := status.issueTimer 367 commonOut.deqPortIdxRead := status.deqPortIdx 368 369 if(params.hasIQWakeUp) { 370 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 371 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 372 if (isComp) 373 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 374 else 375 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 376 } 377 } 378 379 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 380 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 381 if(params.hasIQWakeUp) { 382 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 383 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 384 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 385 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 386 wakeupSrcLoadDependency(srcIdx), 387 status.srcStatus(srcIdx).srcLoadDependency) 388 else status.srcStatus(srcIdx).srcLoadDependency) 389 } 390 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 391 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 392 wakeupSrcLoadDependencyNext(srcIdx), 393 common.srcLoadDependencyNext(srcIdx)) 394 else common.srcLoadDependencyNext(srcIdx)) 395 } 396 } else { 397 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 398 srcLoadDependencyOut := common.srcLoadDependencyNext 399 } 400 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 401 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 402 ldOut := srcLoadDependencyOut(srcIdx) 403 } 404 405 commonOut.enqReady := common.enqReady 406 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 407 commonOut.transEntry.bits := entryUpdate 408 // debug 409 commonOut.entryInValid := commonIn.enq.valid 410 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 411 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 412 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 413 if (params.hasIQWakeUp) { 414 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 415 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 416 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 417 } 418 // vecMem 419 if (params.isVecMemIQ) { 420 commonOut.uopIdx.get := entryReg.payload.uopIdx 421 } 422 } 423 424 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 425 val fromLsq = commonIn.fromLsq.get 426 val vecMemStatus = entryReg.status.vecMem.get 427 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 428 vecMemStatusUpdate := vecMemStatus 429 430 // update blocked 431 entryUpdate.status.blocked := false.B 432 } 433 434 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 435 val origExuOH = 0.U.asTypeOf(exuOH) 436 when(wakeupByIQOH.asUInt.orR) { 437 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 438 }.otherwise { 439 origExuOH := regSrcExuOH 440 } 441 exuOH := 0.U.asTypeOf(exuOH) 442 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 443 } 444 445 object IQFuType { 446 def num = FuType.num 447 448 def apply() = Vec(num, Bool()) 449 450 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 451 val res = 0.U.asTypeOf(fuType) 452 fus.foreach(x => res(x.id) := fuType(x.id)) 453 res 454 } 455 } 456 457 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 458 //wakeup 459 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 460 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 461 //cancel 462 val og0Cancel = Input(ExuOH(backendParams.numExu)) 463 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 464 } 465 466 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 467 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 468 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 469 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 470 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 471 } 472 473 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 474 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 475 wakeup := enqDelayIn.wakeUpFromWB.map(x => x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 476 ).reduce(_ || _) 477 } 478 479 if (params.hasIQWakeUp) { 480 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map( x => 481 x.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 482 ).toIndexedSeq.transpose 483 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 484 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 485 } else { 486 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 487 } 488 489 if (params.hasIQWakeUp) { 490 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 491 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 492 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 493 } 494 } else { 495 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 496 } 497 498 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 499 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 500 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 501 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 502 dp := 1.U << (delay - 1) 503 else 504 dp := ldp << delay 505 } 506 } 507 } 508} 509