1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16 17object EntryBundles extends HasCircularQueuePtrHelper { 18 19 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 20 //basic status 21 val robIdx = new RobPtr 22 val fuType = IQFuType() 23 //src status 24 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 25 //issue status 26 val blocked = Bool() 27 val issued = Bool() 28 val firstIssue = Bool() 29 val issueTimer = UInt(2.W) 30 val deqPortIdx = UInt(1.W) 31 //vector mem status 32 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 55 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 56 //reg cache 57 val useRegCache = Option.when(params.needReadRegCache)(Bool()) 58 val regCacheIdx = Option.when(params.needReadRegCache)(UInt(RegCacheIdxWidth.W)) 59 } 60 61 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 62 val sqIdx = new SqPtr 63 val lqIdx = new LqPtr 64 val numLsElem = NumLsElem() 65 } 66 67 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 68 val robIdx = new RobPtr 69 val resp = RespType() 70 val fuType = FuType() 71 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 72 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 73 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 74 } 75 76 object RespType { 77 def apply() = UInt(2.W) 78 79 def isBlocked(resp: UInt) = { 80 resp === block 81 } 82 83 def succeed(resp: UInt) = { 84 resp === success 85 } 86 87 val block = "b00".U 88 val uncertain = "b01".U 89 val success = "b11".U 90 } 91 92 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val status = new Status() 94 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 95 val payload = new DynInst() 96 } 97 98 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 99 val flush = Flipped(ValidIO(new Redirect)) 100 val enq = Flipped(ValidIO(new EntryBundle)) 101 //wakeup 102 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 103 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 104 // vl 105 val vlIsZero = Input(Bool()) 106 val vlIsVlmax = Input(Bool()) 107 //cancel 108 val og0Cancel = Input(ExuVec()) 109 val og1Cancel = Input(ExuVec()) 110 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 111 //deq sel 112 val deqSel = Input(Bool()) 113 val deqPortIdxWrite = Input(UInt(1.W)) 114 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 115 //trans sel 116 val transSel = Input(Bool()) 117 // vector mem only 118 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 119 val sqDeqPtr = Input(new SqPtr) 120 val lqDeqPtr = Input(new LqPtr) 121 }) 122 } 123 124 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 125 //status 126 val valid = Output(Bool()) 127 val issued = Output(Bool()) 128 val canIssue = Output(Bool()) 129 val fuType = Output(FuType()) 130 val robIdx = Output(new RobPtr) 131 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 132 //src 133 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 134 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 135 //deq 136 val isFirstIssue = Output(Bool()) 137 val entry = ValidIO(new EntryBundle) 138 val cancelBypass = Output(Bool()) 139 val deqPortIdxRead = Output(UInt(1.W)) 140 val issueTimerRead = Output(UInt(2.W)) 141 //trans 142 val enqReady = Output(Bool()) 143 val transEntry = ValidIO(new EntryBundle) 144 // debug 145 val entryInValid = Output(Bool()) 146 val entryOutDeqValid = Output(Bool()) 147 val entryOutTransValid = Output(Bool()) 148 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 149 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 150 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 151 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 152 } 153 154 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 155 val validRegNext = Bool() 156 val flushed = Bool() 157 val clear = Bool() 158 val canIssue = Bool() 159 val enqReady = Bool() 160 val deqSuccess = Bool() 161 val srcWakeup = Vec(params.numRegSrc, Bool()) 162 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 163 val vlWakeupByWb = Bool() 164 val srcCancelVec = Vec(params.numRegSrc, Bool()) 165 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 166 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 167 } 168 169 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 170 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 171 common.flushed := status.robIdx.needFlush(commonIn.flush) 172 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 173 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 174 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 175 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 176 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 177 if (params.numRegSrc == 5) { 178 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 179 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 180 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 181 } 182 else 183 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 184 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 185 common.canIssue := validReg && status.canIssue 186 common.enqReady := !validReg || commonIn.transSel 187 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 188 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 189 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 190 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 191 srcCancel := srcLoadCancel || ldTransCancel 192 } 193 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 194 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 195 } 196 if(isEnq) { 197 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 198 } else { 199 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 200 } 201 if (params.numRegSrc == 5) { 202 // only when numRegSrc == 5 need vl 203 common.vlWakeupByWb := common.srcWakeupByWB(4) 204 } else { 205 common.vlWakeupByWb := false.B 206 } 207 } 208 209 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 210 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 211 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 212 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 213 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 214 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 215 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 216 val canIssueBypass = Bool() 217 } 218 219 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 220 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 221 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 222 if (params.numRegSrc == 5) { 223 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 224 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 225 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 226 } 227 else 228 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 229 }.toSeq.transpose 230 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 231 232 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 233 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 234 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 235 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 236 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 237 case (exuOH, regExuOH) => 238 exuOH := 0.U.asTypeOf(exuOH) 239 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 240 } 241 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 242 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 243 wakeupVec.asUInt.orR | state 244 }).asUInt.andR 245 } 246 247 248 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 249 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 250 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 251 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 252 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 253 case ((dep, originalDep), deqPortIdx) => 254 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 255 dep := 1.U 256 else 257 dep := originalDep << 1 258 } 259 } 260 } 261 262 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 263 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 264 OH.zip(allExuParams).map{case (oh,e) => 265 if (e.isVfExeUnit) oh else false.B 266 }.reduce(_ || _) 267 } 268 269 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 270 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 271 val cancelByLd = common.srcCancelVec.asUInt.orR 272 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 273 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 274 entryUpdate.status.robIdx := status.robIdx 275 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 276 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 277 val cancel = common.srcCancelVec(srcIdx) 278 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 279 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 280 val wakeup = common.srcWakeup(srcIdx) 281 282 val ignoreOldVd = Wire(Bool()) 283 val vlWakeUpByWb = common.vlWakeupByWb 284 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 285 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 286 val vta = entryReg.payload.vpu.vta 287 val vma = entryReg.payload.vpu.vma 288 val vm = entryReg.payload.vpu.vm 289 val vlIsZero = commonIn.vlIsZero 290 val vlIsVlmax = commonIn.vlIsVlmax 291 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 292 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 293 val srcIsVec = SrcType.isVp(srcStatus.srcType) 294 if (params.numVfSrc > 0 && srcIdx == 2) { 295 /** 296 * the src store the old vd, update it when vl is write back 297 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 298 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 299 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 300 */ 301 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 302 } else { 303 ignoreOldVd := false.B 304 } 305 306 srcStatusNext.psrc := srcStatus.psrc 307 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 308 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 309 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 310 // Vf / Mem -> Vf 311 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 312 MuxCase(srcStatus.dataSources.value, Seq( 313 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 314 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 315 srcStatus.dataSources.readBypass -> DataSource.bypass2, 316 srcStatus.dataSources.readBypass2 -> DataSource.reg, 317 )) 318 } 319 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 320 // Vf / Int -> Mem 321 MuxCase(srcStatus.dataSources.value, Seq( 322 wakeupByIQ -> DataSource.bypass, 323 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 324 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 325 srcStatus.dataSources.readBypass2 -> DataSource.reg, 326 )) 327 } 328 else { 329 MuxCase(srcStatus.dataSources.value, Seq( 330 wakeupByIQ -> DataSource.bypass, 331 srcStatus.dataSources.readBypass -> DataSource.reg, 332 )) 333 }) 334 if(params.hasIQWakeUp) { 335 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 336 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 337 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 338 common.srcLoadDependencyNext(srcIdx)) 339 } else { 340 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 341 } 342 343 if (params.needReadRegCache) { 344 val wakeupSrcExuWriteRC = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.needWriteRegCache) 345 val wakeupRC = wakeupSrcExuWriteRC.map(_._1).fold(false.B)(_ || _) && SrcType.isXp(srcStatus.srcType) 346 val wakeupRCIdx = Mux1H(wakeupSrcExuWriteRC.map(_._1), wakeupSrcExuWriteRC.map(_._2.bits.rcDest.get)) 347 val replaceRC = wakeupSrcExuWriteRC.map(x => x._2.bits.rfWen && x._2.bits.rcDest.get === srcStatus.regCacheIdx.get).fold(false.B)(_ || _) 348 349 srcStatusNext.useRegCache.get := MuxCase(srcStatus.useRegCache.get, Seq( 350 cancel -> false.B, 351 wakeupRC -> true.B, 352 replaceRC -> false.B, 353 )) 354 srcStatusNext.regCacheIdx.get := Mux(wakeupRC, wakeupRCIdx, srcStatus.regCacheIdx.get) 355 } 356 } 357 entryUpdate.status.blocked := false.B 358 entryUpdate.status.issued := MuxCase(status.issued, Seq( 359 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 360 commonIn.deqSel -> true.B, 361 !status.srcReady -> false.B, 362 )) 363 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 364 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 365 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 366 entryUpdate.imm.foreach(_ := entryReg.imm.get) 367 entryUpdate.payload := entryReg.payload 368 if (params.isVecMemIQ) { 369 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 370 } 371 } 372 373 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 374 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 375 commonOut.valid := validReg 376 commonOut.issued := entryReg.status.issued 377 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 378 else common.canIssue && !common.flushed) 379 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 380 commonOut.robIdx := status.robIdx 381 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 382 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 383 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 384 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 385 val useRegCache = status.srcStatus(srcIdx).useRegCache.getOrElse(false.B) && status.srcStatus(srcIdx).dataSources.readReg 386 dataSourceOut.value := (if (isComp) 387 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 388 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 389 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 390 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 391 )) 392 } else { 393 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 394 wakeupByIQWithoutCancel -> DataSource.forward, 395 useRegCache -> DataSource.regcache, 396 )) 397 } 398 else { 399 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 400 useRegCache -> DataSource.regcache, 401 )) 402 }) 403 } 404 commonOut.isFirstIssue := !status.firstIssue 405 commonOut.entry.valid := validReg 406 commonOut.entry.bits := entryReg 407 if(isEnq) { 408 commonOut.entry.bits.status := status 409 } 410 commonOut.issueTimerRead := status.issueTimer 411 commonOut.deqPortIdxRead := status.deqPortIdx 412 413 if(params.hasIQWakeUp) { 414 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 415 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 416 if (isComp) 417 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 418 else 419 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 420 } 421 } 422 423 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 424 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 425 if(params.hasIQWakeUp) { 426 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 427 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 428 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 429 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 430 wakeupSrcLoadDependency(srcIdx), 431 status.srcStatus(srcIdx).srcLoadDependency) 432 else status.srcStatus(srcIdx).srcLoadDependency) 433 } 434 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 435 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 436 wakeupSrcLoadDependencyNext(srcIdx), 437 common.srcLoadDependencyNext(srcIdx)) 438 else common.srcLoadDependencyNext(srcIdx)) 439 } 440 } else { 441 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 442 srcLoadDependencyOut := common.srcLoadDependencyNext 443 } 444 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 445 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 446 ldOut := srcLoadDependencyOut(srcIdx) 447 } 448 449 commonOut.enqReady := common.enqReady 450 commonOut.transEntry.valid := validReg && !common.flushed && !status.issued 451 commonOut.transEntry.bits := entryUpdate 452 // debug 453 commonOut.entryInValid := commonIn.enq.valid 454 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 455 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 456 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 457 if (params.hasIQWakeUp) { 458 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 459 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 460 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 461 } 462 // vecMem 463 if (params.isVecMemIQ) { 464 commonOut.uopIdx.get := entryReg.payload.uopIdx 465 } 466 } 467 468 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 469 val fromLsq = commonIn.fromLsq.get 470 val vecMemStatus = entryReg.status.vecMem.get 471 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 472 vecMemStatusUpdate := vecMemStatus 473 474 // update blocked 475 entryUpdate.status.blocked := false.B 476 } 477 478 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 479 val origExuOH = Wire(chiselTypeOf(exuOH)) 480 when(wakeupByIQOH.asUInt.orR) { 481 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 482 }.otherwise { 483 origExuOH := regSrcExuOH 484 } 485 exuOH := 0.U.asTypeOf(exuOH) 486 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 487 } 488 489 object IQFuType { 490 def num = FuType.num 491 492 def apply() = Vec(num, Bool()) 493 494 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 495 val res = WireDefault(0.U.asTypeOf(fuType)) 496 fus.foreach(x => res(x.id) := fuType(x.id)) 497 res 498 } 499 } 500 501 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 502 //wakeup 503 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 504 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 505 //cancel 506 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 507 val og0Cancel = Input(ExuVec()) 508 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 509 } 510 511 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 512 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 513 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 514 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 515 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 516 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 517 } 518 519 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 520 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 521 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 522 if (i == 3) 523 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 524 else if (i == 4) 525 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 526 else 527 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 528 }.reduce(_ || _) 529 } 530 531 if (params.hasIQWakeUp) { 532 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 533 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 534 if (params.numRegSrc == 5) { 535 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 536 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 537 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 538 } 539 else 540 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 541 }.toIndexedSeq.transpose 542 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 543 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 544 } else { 545 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 546 } 547 548 if (params.hasIQWakeUp) { 549 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 550 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 551 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 552 } 553 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 554 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 555 } 556 } else { 557 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 558 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 559 } 560 561 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 562 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 563 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 564 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 565 dp := 1.U << (delay - 1) 566 else 567 dp := ldp << delay 568 } 569 } 570 } 571} 572