1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16 17object EntryBundles extends HasCircularQueuePtrHelper { 18 19 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 20 //basic status 21 val robIdx = new RobPtr 22 val fuType = IQFuType() 23 //src status 24 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 25 //issue status 26 val blocked = Bool() 27 val issued = Bool() 28 val firstIssue = Bool() 29 val issueTimer = UInt(2.W) 30 val deqPortIdx = UInt(1.W) 31 //vector mem status 32 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 55 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 56 //reg cache 57 val useRegCache = Option.when(params.needReadRegCache)(Bool()) 58 val regCacheIdx = Option.when(params.needReadRegCache)(UInt(RegCacheIdxWidth.W)) 59 } 60 61 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 62 val sqIdx = new SqPtr 63 val lqIdx = new LqPtr 64 val numLsElem = NumLsElem() 65 } 66 67 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 68 val robIdx = new RobPtr 69 val resp = RespType() 70 val fuType = FuType() 71 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 72 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 73 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 74 } 75 76 object RespType { 77 def apply() = UInt(2.W) 78 79 def isBlocked(resp: UInt) = { 80 resp === block 81 } 82 83 def succeed(resp: UInt) = { 84 resp === success 85 } 86 87 val block = "b00".U 88 val uncertain = "b01".U 89 val success = "b11".U 90 } 91 92 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val status = new Status() 94 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 95 val payload = new DynInst() 96 } 97 98 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 99 val flush = Flipped(ValidIO(new Redirect)) 100 val enq = Flipped(ValidIO(new EntryBundle)) 101 //wakeup 102 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 103 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 104 // vl 105 val vlIsZero = Input(Bool()) 106 val vlIsVlmax = Input(Bool()) 107 //cancel 108 val og0Cancel = Input(ExuVec()) 109 val og1Cancel = Input(ExuVec()) 110 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 111 //deq sel 112 val deqSel = Input(Bool()) 113 val deqPortIdxWrite = Input(UInt(1.W)) 114 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 115 //trans sel 116 val transSel = Input(Bool()) 117 // vector mem only 118 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 119 val sqDeqPtr = Input(new SqPtr) 120 val lqDeqPtr = Input(new LqPtr) 121 }) 122 } 123 124 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 125 //status 126 val valid = Output(Bool()) 127 val canIssue = Output(Bool()) 128 val fuType = Output(FuType()) 129 val robIdx = Output(new RobPtr) 130 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 131 //src 132 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 133 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 134 //deq 135 val isFirstIssue = Output(Bool()) 136 val entry = ValidIO(new EntryBundle) 137 val cancelBypass = Output(Bool()) 138 val deqPortIdxRead = Output(UInt(1.W)) 139 val issueTimerRead = Output(UInt(2.W)) 140 //trans 141 val enqReady = Output(Bool()) 142 val transEntry = ValidIO(new EntryBundle) 143 // debug 144 val entryInValid = Output(Bool()) 145 val entryOutDeqValid = Output(Bool()) 146 val entryOutTransValid = Output(Bool()) 147 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 148 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 149 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 150 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 151 } 152 153 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 154 val validRegNext = Bool() 155 val flushed = Bool() 156 val clear = Bool() 157 val canIssue = Bool() 158 val enqReady = Bool() 159 val deqSuccess = Bool() 160 val srcWakeup = Vec(params.numRegSrc, Bool()) 161 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 162 val vlWakeupByWb = Bool() 163 val srcCancelVec = Vec(params.numRegSrc, Bool()) 164 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 165 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 166 } 167 168 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 169 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 170 common.flushed := status.robIdx.needFlush(commonIn.flush) 171 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 172 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 173 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 174 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 175 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 176 if (params.numRegSrc == 5) { 177 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 178 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 179 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 180 } 181 else 182 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 183 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 184 common.canIssue := validReg && status.canIssue 185 common.enqReady := !validReg || commonIn.transSel 186 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 187 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 188 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 189 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 190 srcCancel := srcLoadCancel || ldTransCancel 191 } 192 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 193 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 194 } 195 if(isEnq) { 196 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 197 } else { 198 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 199 } 200 if (params.numRegSrc == 5) { 201 // only when numRegSrc == 5 need vl 202 common.vlWakeupByWb := common.srcWakeupByWB(4) 203 } else { 204 common.vlWakeupByWb := false.B 205 } 206 } 207 208 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 209 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 210 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 211 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 212 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 213 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 214 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 215 val canIssueBypass = Bool() 216 } 217 218 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 219 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 220 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 221 if (params.numRegSrc == 5) { 222 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 223 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 224 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 225 } 226 else 227 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 228 }.toSeq.transpose 229 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 230 231 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 232 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 233 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 234 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 235 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 236 case (exuOH, regExuOH) => 237 exuOH := 0.U.asTypeOf(exuOH) 238 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 239 } 240 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 241 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 242 wakeupVec.asUInt.orR | state 243 }).asUInt.andR 244 } 245 246 247 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 248 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 249 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 250 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 251 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 252 case ((dep, originalDep), deqPortIdx) => 253 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 254 dep := 1.U 255 else 256 dep := originalDep << 1 257 } 258 } 259 } 260 261 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 262 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 263 OH.zip(allExuParams).map{case (oh,e) => 264 if (e.isVfExeUnit) oh else false.B 265 }.reduce(_ || _) 266 } 267 268 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 269 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 270 val cancelByLd = common.srcCancelVec.asUInt.orR 271 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 272 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 273 entryUpdate.status.robIdx := status.robIdx 274 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 275 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 276 val cancel = common.srcCancelVec(srcIdx) 277 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 278 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 279 val wakeup = common.srcWakeup(srcIdx) 280 281 val ignoreOldVd = Wire(Bool()) 282 val vlWakeUpByWb = common.vlWakeupByWb 283 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 284 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 285 val vta = entryReg.payload.vpu.vta 286 val vma = entryReg.payload.vpu.vma 287 val vm = entryReg.payload.vpu.vm 288 val vlIsZero = commonIn.vlIsZero 289 val vlIsVlmax = commonIn.vlIsVlmax 290 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 291 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 292 val srcIsVec = SrcType.isVp(srcStatus.srcType) 293 if (params.numVfSrc > 0 && srcIdx == 2) { 294 /** 295 * the src store the old vd, update it when vl is write back 296 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 297 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 298 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 299 */ 300 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 301 } else { 302 ignoreOldVd := false.B 303 } 304 305 srcStatusNext.psrc := srcStatus.psrc 306 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 307 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 308 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 309 // Vf / Mem -> Vf 310 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 311 MuxCase(srcStatus.dataSources.value, Seq( 312 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 313 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 314 srcStatus.dataSources.readBypass -> DataSource.bypass2, 315 srcStatus.dataSources.readBypass2 -> DataSource.reg, 316 )) 317 } 318 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 319 // Vf / Int -> Mem 320 MuxCase(srcStatus.dataSources.value, Seq( 321 wakeupByIQ -> DataSource.bypass, 322 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 323 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 324 srcStatus.dataSources.readBypass2 -> DataSource.reg, 325 )) 326 } 327 else { 328 MuxCase(srcStatus.dataSources.value, Seq( 329 wakeupByIQ -> DataSource.bypass, 330 srcStatus.dataSources.readBypass -> DataSource.reg, 331 )) 332 }) 333 if(params.hasIQWakeUp) { 334 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 335 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 336 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 337 common.srcLoadDependencyNext(srcIdx)) 338 } else { 339 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 340 } 341 342 if (params.needReadRegCache) { 343 val wakeupSrcExuWriteRC = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.needWriteRegCache) 344 val wakeupRC = wakeupSrcExuWriteRC.map(_._1).fold(false.B)(_ || _) && SrcType.isXp(srcStatus.srcType) 345 val wakeupRCIdx = Mux1H(wakeupSrcExuWriteRC.map(_._1), wakeupSrcExuWriteRC.map(_._2.bits.rcDest.get)) 346 val replaceRC = wakeupSrcExuWriteRC.map(x => x._2.bits.rfWen && x._2.bits.rcDest.get === srcStatus.regCacheIdx.get).fold(false.B)(_ || _) 347 348 srcStatusNext.useRegCache.get := MuxCase(srcStatus.useRegCache.get, Seq( 349 cancel -> false.B, 350 wakeupRC -> true.B, 351 replaceRC -> false.B, 352 )) 353 srcStatusNext.regCacheIdx.get := Mux(wakeupRC, wakeupRCIdx, srcStatus.regCacheIdx.get) 354 } 355 } 356 entryUpdate.status.blocked := false.B 357 entryUpdate.status.issued := MuxCase(status.issued, Seq( 358 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 359 commonIn.deqSel -> true.B, 360 !status.srcReady -> false.B, 361 )) 362 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 363 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 364 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 365 entryUpdate.imm.foreach(_ := entryReg.imm.get) 366 entryUpdate.payload := entryReg.payload 367 if (params.isVecMemIQ) { 368 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 369 } 370 } 371 372 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 373 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 374 commonOut.valid := validReg 375 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 376 else common.canIssue && !common.flushed) 377 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 378 commonOut.robIdx := status.robIdx 379 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 380 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 381 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 382 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 383 val useRegCache = status.srcStatus(srcIdx).useRegCache.getOrElse(false.B) && status.srcStatus(srcIdx).dataSources.readReg 384 dataSourceOut.value := (if (isComp) 385 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 386 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 387 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 388 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 389 )) 390 } else { 391 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 392 wakeupByIQWithoutCancel -> DataSource.forward, 393 useRegCache -> DataSource.regcache, 394 )) 395 } 396 else { 397 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 398 useRegCache -> DataSource.regcache, 399 )) 400 }) 401 } 402 commonOut.isFirstIssue := !status.firstIssue 403 commonOut.entry.valid := validReg 404 commonOut.entry.bits := entryReg 405 if(isEnq) { 406 commonOut.entry.bits.status := status 407 } 408 commonOut.issueTimerRead := status.issueTimer 409 commonOut.deqPortIdxRead := status.deqPortIdx 410 411 if(params.hasIQWakeUp) { 412 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 413 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 414 if (isComp) 415 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 416 else 417 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 418 } 419 } 420 421 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 422 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 423 if(params.hasIQWakeUp) { 424 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 425 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 426 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 427 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 428 wakeupSrcLoadDependency(srcIdx), 429 status.srcStatus(srcIdx).srcLoadDependency) 430 else status.srcStatus(srcIdx).srcLoadDependency) 431 } 432 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 433 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 434 wakeupSrcLoadDependencyNext(srcIdx), 435 common.srcLoadDependencyNext(srcIdx)) 436 else common.srcLoadDependencyNext(srcIdx)) 437 } 438 } else { 439 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 440 srcLoadDependencyOut := common.srcLoadDependencyNext 441 } 442 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 443 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 444 ldOut := srcLoadDependencyOut(srcIdx) 445 } 446 447 commonOut.enqReady := common.enqReady 448 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 449 commonOut.transEntry.bits := entryUpdate 450 // debug 451 commonOut.entryInValid := commonIn.enq.valid 452 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 453 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 454 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 455 if (params.hasIQWakeUp) { 456 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 457 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 458 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 459 } 460 // vecMem 461 if (params.isVecMemIQ) { 462 commonOut.uopIdx.get := entryReg.payload.uopIdx 463 } 464 } 465 466 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 467 val fromLsq = commonIn.fromLsq.get 468 val vecMemStatus = entryReg.status.vecMem.get 469 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 470 vecMemStatusUpdate := vecMemStatus 471 472 // update blocked 473 entryUpdate.status.blocked := false.B 474 } 475 476 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 477 val origExuOH = Wire(chiselTypeOf(exuOH)) 478 when(wakeupByIQOH.asUInt.orR) { 479 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 480 }.otherwise { 481 origExuOH := regSrcExuOH 482 } 483 exuOH := 0.U.asTypeOf(exuOH) 484 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 485 } 486 487 object IQFuType { 488 def num = FuType.num 489 490 def apply() = Vec(num, Bool()) 491 492 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 493 val res = WireDefault(0.U.asTypeOf(fuType)) 494 fus.foreach(x => res(x.id) := fuType(x.id)) 495 res 496 } 497 } 498 499 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 500 //wakeup 501 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 502 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 503 //cancel 504 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 505 val og0Cancel = Input(ExuVec()) 506 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 507 } 508 509 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 510 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 511 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 512 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 513 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 514 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 515 } 516 517 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 518 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 519 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 520 if (i == 3) 521 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 522 else if (i == 4) 523 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 524 else 525 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 526 }.reduce(_ || _) 527 } 528 529 if (params.hasIQWakeUp) { 530 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 531 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 532 if (params.numRegSrc == 5) { 533 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 534 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 535 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 536 } 537 else 538 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 539 }.toIndexedSeq.transpose 540 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 541 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 542 } else { 543 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 544 } 545 546 if (params.hasIQWakeUp) { 547 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 548 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 549 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 550 } 551 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 552 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 553 } 554 } else { 555 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 556 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 557 } 558 559 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 560 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 561 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 562 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 563 dp := 1.U << (delay - 1) 564 else 565 dp := ldp << delay 566 } 567 } 568 } 569} 570