1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, HasDCacheParameters, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 31import xiangshan.backend.fu.util.SdtrigExt 32 33class AtomicsUnit(implicit p: Parameters) extends XSModule 34 with MemoryOpConstants 35 with HasDCacheParameters 36 with SdtrigExt{ 37 val io = IO(new Bundle() { 38 val hartId = Input(UInt(hartIdLen.W)) 39 val in = Flipped(Decoupled(new MemExuInput)) 40 val storeDataIn = Flipped(Valid(new MemExuOutput)) // src2 from rs 41 val out = Decoupled(new MemExuOutput) 42 val dcache = new AtomicWordIO 43 val dtlb = new TlbRequestIO(2) 44 val pmpResp = Flipped(new PMPRespBundle()) 45 val flush_sbuffer = new SbufferFlushBundle 46 val feedbackSlow = ValidIO(new RSFeedback) 47 val redirect = Flipped(ValidIO(new Redirect)) 48 val exceptionAddr = ValidIO(new Bundle { 49 val vaddr = UInt(VAddrBits.W) 50 val gpaddr = UInt(GPAddrBits.W) 51 }) 52 val csrCtrl = Flipped(new CustomCSRCtrlIO) 53 }) 54 55 //------------------------------------------------------- 56 // Atomics Memory Accsess FSM 57 //------------------------------------------------------- 58 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 59 val state = RegInit(s_invalid) 60 val out_valid = RegInit(false.B) 61 val data_valid = RegInit(false.B) 62 val in = Reg(new MemExuInput()) 63 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 64 val atom_override_xtval = RegInit(false.B) 65 val have_sent_first_tlb_req = RegInit(false.B) 66 val isLr = in.uop.fuOpType === LSUOpType.lr_w || in.uop.fuOpType === LSUOpType.lr_d 67 // paddr after translation 68 val paddr = Reg(UInt()) 69 val gpaddr = Reg(UInt()) 70 val vaddr = in.src(0) 71 val is_mmio = Reg(Bool()) 72 73 // dcache response data 74 val resp_data = Reg(UInt()) 75 val resp_data_wire = WireInit(0.U) 76 val is_lrsc_valid = Reg(Bool()) 77 // sbuffer is empty or not 78 val sbuffer_empty = io.flush_sbuffer.empty 79 80 81 // Difftest signals 82 val paddr_reg = Reg(UInt(64.W)) 83 val data_reg = Reg(UInt(64.W)) 84 val mask_reg = Reg(UInt(8.W)) 85 val fuop_reg = Reg(UInt(8.W)) 86 87 io.exceptionAddr.valid := atom_override_xtval 88 io.exceptionAddr.bits.vaddr := in.src(0) 89 io.exceptionAddr.bits.gpaddr := gpaddr 90 91 // assign default value to output signals 92 io.in.ready := false.B 93 94 io.dcache.req.valid := false.B 95 io.dcache.req.bits := DontCare 96 97 io.dtlb.req.valid := false.B 98 io.dtlb.req.bits := DontCare 99 io.dtlb.req_kill := false.B 100 io.dtlb.resp.ready := true.B 101 102 io.flush_sbuffer.valid := false.B 103 104 XSDebug("state: %d\n", state) 105 106 when (state === s_invalid) { 107 io.in.ready := true.B 108 when (io.in.fire) { 109 in := io.in.bits 110 in.src(1) := in.src(1) // leave src2 unchanged 111 state := s_tlb_and_flush_sbuffer_req 112 have_sent_first_tlb_req := false.B 113 } 114 } 115 116 when (io.storeDataIn.fire) { 117 in.src(1) := io.storeDataIn.bits.data 118 data_valid := true.B 119 } 120 121 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 122 123 // Send TLB feedback to store issue queue 124 // we send feedback right after we receives request 125 // also, we always treat amo as tlb hit 126 // since we will continue polling tlb all by ourself 127 io.feedbackSlow.valid := GatedValidRegNext(GatedValidRegNext(io.in.valid)) 128 io.feedbackSlow.bits.hit := true.B 129 io.feedbackSlow.bits.robIdx := RegEnable(io.in.bits.uop.robIdx, io.in.valid) 130 io.feedbackSlow.bits.sqIdx := RegEnable(io.in.bits.uop.sqIdx, io.in.valid) 131 io.feedbackSlow.bits.lqIdx := RegEnable(io.in.bits.uop.lqIdx, io.in.valid) 132 io.feedbackSlow.bits.flushState := DontCare 133 io.feedbackSlow.bits.sourceType := DontCare 134 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 135 136 // tlb translation, manipulating signals && deal with exception 137 // at the same time, flush sbuffer 138 when (state === s_tlb_and_flush_sbuffer_req) { 139 // send req to dtlb 140 // keep firing until tlb hit 141 io.dtlb.req.valid := true.B 142 io.dtlb.req.bits.vaddr := in.src(0) 143 io.dtlb.resp.ready := true.B 144 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 145 io.dtlb.req.bits.debug.pc := in.uop.pc 146 io.dtlb.req.bits.debug.robIdx := in.uop.robIdx 147 io.dtlb.req.bits.debug.isFirstIssue := false.B 148 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() // FIXME lyq: it will be always assigned 149 150 // send req to sbuffer to flush it if it is not empty 151 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 152 153 // do not accept tlb resp in the first cycle 154 // this limition is for hw prefetcher 155 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 156 have_sent_first_tlb_req := true.B 157 158 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 159 paddr := io.dtlb.resp.bits.paddr(0) 160 gpaddr := io.dtlb.resp.bits.gpaddr(0) 161 // exception handling 162 val addrAligned = LookupTree(in.uop.fuOpType(1,0), List( 163 "b00".U -> true.B, //b 164 "b01".U -> (in.src(0)(0) === 0.U), //h 165 "b10".U -> (in.src(0)(1,0) === 0.U), //w 166 "b11".U -> (in.src(0)(2,0) === 0.U) //d 167 )) 168 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 169 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 170 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 171 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 172 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 173 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 174 exceptionVec(storeGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.st 175 exceptionVec(loadGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.ld 176 177 when (!io.dtlb.resp.bits.miss) { 178 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 179 when (!addrAligned) { 180 // NOTE: when addrAligned, do not need to wait tlb actually 181 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 182 // if there are exceptions, no need to execute it 183 state := s_finish 184 out_valid := true.B 185 atom_override_xtval := true.B 186 } .otherwise { 187 state := s_pm 188 } 189 } 190 } 191 } 192 193 when (state === s_pm) { 194 val pmp = WireInit(io.pmpResp) 195 is_mmio := pmp.mmio 196 197 // NOTE: only handle load/store exception here, if other exception happens, don't send here 198 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 199 exceptionVec(storeGuestPageFault) || exceptionVec(loadGuestPageFault) || 200 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 201 val exception_pa = pmp.st || pmp.ld 202 when (exception_va || exception_pa) { 203 state := s_finish 204 out_valid := true.B 205 atom_override_xtval := true.B 206 }.otherwise { 207 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 208 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 209 } 210 // update storeAccessFault bit 211 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 212 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 213 } 214 215 when (state === s_wait_flush_sbuffer_resp) { 216 when (sbuffer_empty) { 217 state := s_cache_req 218 } 219 } 220 221 when (state === s_cache_req) { 222 val pipe_req = io.dcache.req.bits 223 pipe_req := DontCare 224 225 pipe_req.cmd := LookupTree(in.uop.fuOpType, List( 226 LSUOpType.lr_w -> M_XLR, 227 LSUOpType.sc_w -> M_XSC, 228 LSUOpType.amoswap_w -> M_XA_SWAP, 229 LSUOpType.amoadd_w -> M_XA_ADD, 230 LSUOpType.amoxor_w -> M_XA_XOR, 231 LSUOpType.amoand_w -> M_XA_AND, 232 LSUOpType.amoor_w -> M_XA_OR, 233 LSUOpType.amomin_w -> M_XA_MIN, 234 LSUOpType.amomax_w -> M_XA_MAX, 235 LSUOpType.amominu_w -> M_XA_MINU, 236 LSUOpType.amomaxu_w -> M_XA_MAXU, 237 238 LSUOpType.lr_d -> M_XLR, 239 LSUOpType.sc_d -> M_XSC, 240 LSUOpType.amoswap_d -> M_XA_SWAP, 241 LSUOpType.amoadd_d -> M_XA_ADD, 242 LSUOpType.amoxor_d -> M_XA_XOR, 243 LSUOpType.amoand_d -> M_XA_AND, 244 LSUOpType.amoor_d -> M_XA_OR, 245 LSUOpType.amomin_d -> M_XA_MIN, 246 LSUOpType.amomax_d -> M_XA_MAX, 247 LSUOpType.amominu_d -> M_XA_MINU, 248 LSUOpType.amomaxu_d -> M_XA_MAXU 249 )) 250 pipe_req.miss := false.B 251 pipe_req.probe := false.B 252 pipe_req.probe_need_data := false.B 253 pipe_req.source := AMO_SOURCE.U 254 pipe_req.addr := get_block_addr(paddr) 255 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 256 pipe_req.word_idx := get_word(paddr) 257 pipe_req.amo_data := genWdata(in.src(1), in.uop.fuOpType(1,0)) 258 pipe_req.amo_mask := genWmask(paddr, in.uop.fuOpType(1,0)) 259 260 io.dcache.req.valid := Mux( 261 io.dcache.req.bits.cmd === M_XLR, 262 !io.dcache.block_lr, // block lr to survive in lr storm 263 data_valid // wait until src(1) is ready 264 ) 265 266 when(io.dcache.req.fire){ 267 state := s_cache_resp 268 paddr_reg := paddr 269 data_reg := io.dcache.req.bits.amo_data 270 mask_reg := io.dcache.req.bits.amo_mask 271 fuop_reg := in.uop.fuOpType 272 } 273 } 274 275 val dcache_resp_data = Reg(UInt()) 276 val dcache_resp_id = Reg(UInt()) 277 val dcache_resp_error = Reg(Bool()) 278 279 when (state === s_cache_resp) { 280 // when not miss 281 // everything is OK, simply send response back to sbuffer 282 // when miss and not replay 283 // wait for missQueue to handling miss and replaying our request 284 // when miss and replay 285 // req missed and fail to enter missQueue, manually replay it later 286 // TODO: add assertions: 287 // 1. add a replay delay counter? 288 // 2. when req gets into MissQueue, it should not miss any more 289 when(io.dcache.resp.fire) { 290 when(io.dcache.resp.bits.miss) { 291 when(io.dcache.resp.bits.replay) { 292 state := s_cache_req 293 } 294 } .otherwise { 295 dcache_resp_data := io.dcache.resp.bits.data 296 dcache_resp_id := io.dcache.resp.bits.id 297 dcache_resp_error := io.dcache.resp.bits.error 298 state := s_cache_resp_latch 299 } 300 } 301 } 302 303 when (state === s_cache_resp_latch) { 304 is_lrsc_valid := dcache_resp_id 305 val rdataSel = LookupTree(paddr(2, 0), List( 306 "b000".U -> dcache_resp_data(63, 0), 307 "b001".U -> dcache_resp_data(63, 8), 308 "b010".U -> dcache_resp_data(63, 16), 309 "b011".U -> dcache_resp_data(63, 24), 310 "b100".U -> dcache_resp_data(63, 32), 311 "b101".U -> dcache_resp_data(63, 40), 312 "b110".U -> dcache_resp_data(63, 48), 313 "b111".U -> dcache_resp_data(63, 56) 314 )) 315 316 resp_data_wire := LookupTree(in.uop.fuOpType, List( 317 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 318 LSUOpType.sc_w -> dcache_resp_data, 319 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 320 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 321 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 322 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 323 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 324 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 325 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 326 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 327 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 328 329 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 330 LSUOpType.sc_d -> dcache_resp_data, 331 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 332 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 333 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 334 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 335 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 336 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 337 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 338 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 339 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 340 )) 341 342 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 343 exceptionVec(loadAccessFault) := isLr 344 exceptionVec(storeAccessFault) := !isLr 345 assert(!exceptionVec(loadAccessFault)) 346 assert(!exceptionVec(storeAccessFault)) 347 } 348 349 resp_data := resp_data_wire 350 state := s_finish 351 out_valid := true.B 352 } 353 354 io.out.valid := out_valid 355 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 356 io.out.bits := DontCare 357 io.out.bits.uop := in.uop 358 io.out.bits.uop.exceptionVec := exceptionVec 359 io.out.bits.data := resp_data 360 io.out.bits.debug.isMMIO := is_mmio 361 io.out.bits.debug.paddr := paddr 362 when (io.out.fire) { 363 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data) 364 state := s_invalid 365 out_valid := false.B 366 } 367 368 when (state === s_finish) { 369 data_valid := false.B 370 } 371 372 when (io.redirect.valid) { 373 atom_override_xtval := false.B 374 } 375 376 /* 377 // atomic trigger 378 val csrCtrl = io.csrCtrl 379 val tdata = Reg(Vec(TriggerNum, new MatchTriggerIO)) 380 val tEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 381 tEnableVec := csrCtrl.mem_trigger.tEnableVec 382 when(csrCtrl.mem_trigger.tUpdate.valid) { 383 tdata(csrCtrl.mem_trigger.tUpdate.bits.addr) := csrCtrl.mem_trigger.tUpdate.bits.tdata 384 } 385 386 val backendTriggerTimingVec = VecInit(tdata.map(_.timing)) 387 val backendTriggerChainVec = VecInit(tdata.map(_.chain)) 388 val backendTriggerHitVec = WireInit(VecInit(Seq.fill(TriggerNum)(false.B))) 389 val backendTriggerCanFireVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 390 391 when(state === s_cache_req) { 392 // store trigger 393 val store_hit = Wire(Vec(TriggerNum, Bool())) 394 for (j <- 0 until TriggerNum) { 395 store_hit(j) := !tdata(j).select && TriggerCmp( 396 vaddr, 397 tdata(j).tdata2, 398 tdata(j).matchType, 399 tEnableVec(j) && tdata(j).store 400 ) 401 } 402 // load trigger 403 val load_hit = Wire(Vec(TriggerNum, Bool())) 404 for (j <- 0 until TriggerNum) { 405 load_hit(j) := !tdata(j).select && TriggerCmp( 406 vaddr, 407 tdata(j).tdata2, 408 tdata(j).matchType, 409 tEnableVec(j) && tdata(j).load 410 ) 411 } 412 backendTriggerHitVec := store_hit.zip(load_hit).map { case (sh, lh) => sh || lh } 413 // triggerCanFireVec will update at T+1 414 TriggerCheckCanFire(TriggerNum, backendTriggerCanFireVec, backendTriggerHitVec, backendTriggerTimingVec, backendTriggerChainVec) 415 } 416 417 // addr trigger do cmp at s_cache_req 418 // trigger result is used at s_finish 419 // thus we can delay it safely 420 io.out.bits.uop.trigger.backendHit := backendTriggerHitVec 421 io.out.bits.uop.trigger.backendCanFire := backendTriggerCanFireVec 422 423 */ 424 425 if (env.EnableDifftest) { 426 val difftest = DifftestModule(new DiffAtomicEvent) 427 difftest.coreid := io.hartId 428 difftest.valid := state === s_cache_resp_latch 429 difftest.addr := paddr_reg 430 difftest.data := data_reg 431 difftest.mask := mask_reg 432 difftest.fuop := fuop_reg 433 difftest.out := resp_data_wire 434 } 435 436 if (env.EnableDifftest || env.AlwaysBasicDiff) { 437 val uop = io.out.bits.uop 438 val difftest = DifftestModule(new DiffLrScEvent) 439 difftest.coreid := io.hartId 440 difftest.valid := io.out.fire && 441 (uop.fuOpType === LSUOpType.sc_d || uop.fuOpType === LSUOpType.sc_w) 442 difftest.success := is_lrsc_valid 443 } 444} 445