1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0), 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 immType : Set[UInt] = Set(), 67 // vector 68 vconfigWakeUp : Boolean = false, 69 maskWakeUp : Boolean = false, 70) { 71 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 72 def needFpWen: Boolean = writeFpRf 73 def needVecWen: Boolean = writeVecRf 74 var vconfigIdx = -1 75 var maskSrcIdx = -1 76 if (vconfigWakeUp) { 77 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 78 } 79 if (maskWakeUp) { 80 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 81 } 82 83 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 84 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 85 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 86 87 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 88 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 93 94 def readFp: Boolean = numFpSrc > 0 95 96 def fuSel(uop: ExuInput): Bool = { 97 // Don't add more shit here!!! 98 // Todo: add new FuType to distinguish f2i, f2f 99 uop.fuType === this.fuType.U 100 } 101 102 /** 103 * params(i): data type set of the ith src port 104 * @return 105 */ 106 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 107 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 108 // make srcData is uniform sized to avoid exception when transpose 109 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 110 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 111 } 112 113 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 114 srcData 115 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 116 .filter(_.nonEmpty) 117 .map(_.get) 118 .toSet 119 } 120 121 def hasNoDataWB: Boolean = { 122 !(writeIntRf || writeFpRf || writeVecRf) 123 } 124 125 def getSrcMaxWidthVec = { 126 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 127 } 128 129 def genSrcDataVec: Seq[UInt] = { 130 getSrcMaxWidthVec.map(w => UInt(w.W)) 131 } 132 133 // csr's redirect is in its exception bundle 134 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 135 136 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 137 138 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 139 140 // predict info 141 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 142 143 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 144 145 def needFPUCtrl: Boolean = { 146 import FuType._ 147 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 148 } 149 150 def needVecCtrl: Boolean = { 151 import FuType._ 152 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 153 } 154 155 def isMul: Boolean = fuType == FuType.mul 156 157 def isDiv: Boolean = fuType == FuType.div 158 159 def isCsr: Boolean = fuType == FuType.csr 160 161 def isFence: Boolean = fuType == FuType.fence 162 163 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 164 fuType == FuType.vppu || fuType == FuType.vipu || 165 fuType == FuType.vfalu || fuType == FuType.vfma || 166 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 167 fuType == FuType.vidiv 168 169 def isSta: Boolean = name.contains("sta") 170 171 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 172 fuType == FuType.fmisc || fuType == FuType.div || 173 fuType == FuType.vfdiv || fuType == FuType.vidiv 174 175 /** 176 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 177 * @param data [[DataConfig]] 178 * @param tips tips if get failed 179 * @return the index of special src data 180 */ 181 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 182 val srcIdxVec = srcData.map(x => x.indexOf(data)) 183 val idx0 = srcIdxVec.head 184 for (idx <- srcIdxVec) { 185 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 186 } 187 idx0 188 } 189 190 override def toString: String = { 191 var str = s"${this.name}: " 192 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 193 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 194 str += s"latency($latency)" 195 str += s"src($srcData)" 196 str 197 } 198} 199 200object FuConfig { 201 val JmpCfg: FuConfig = FuConfig ( 202 name = "jmp", 203 fuType = FuType.jmp, 204 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 205 srcData = Seq( 206 Seq(IntData()), // jal 207 ), 208 piped = true, 209 writeIntRf = true, 210 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 211 ) 212 213 val BrhCfg: FuConfig = FuConfig ( 214 name = "brh", 215 fuType = FuType.brh, 216 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 217 srcData = Seq( 218 Seq(IntData(), IntData()), 219 ), 220 piped = true, 221 immType = Set(SelImm.IMM_SB), 222 ) 223 224 val I2fCfg: FuConfig = FuConfig ( 225 name = "i2f", 226 FuType.i2f, 227 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 228 srcData = Seq( 229 Seq(IntData()), 230 ), 231 piped = true, 232 writeFpRf = true, 233 writeFflags = true, 234 latency = CertainLatency(2), 235 needSrcFrm = true, 236 ) 237 238 val I2vCfg: FuConfig = FuConfig ( 239 name = "i2v", 240 FuType.i2v, 241 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 242 srcData = Seq( 243 Seq(IntData(), IntData()), 244 ), 245 piped = true, 246 writeVecRf = true, 247 latency = CertainLatency(0), 248 dataBits = 128, 249 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 250 ) 251 252 val F2vCfg: FuConfig = FuConfig ( 253 name = "f2v", 254 FuType.f2v, 255 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 256 srcData = Seq( 257 Seq(FpData(), FpData()), 258 Seq(FpData()), 259 ), 260 piped = true, 261 writeVecRf = true, 262 latency = CertainLatency(0), 263 dataBits = 128, 264 ) 265 266 val CsrCfg: FuConfig = FuConfig ( 267 name = "csr", 268 fuType = FuType.csr, 269 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 270 srcData = Seq( 271 Seq(IntData()), 272 ), 273 piped = true, 274 writeIntRf = true, 275 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 276 flushPipe = true, 277 ) 278 279 val AluCfg: FuConfig = FuConfig ( 280 name = "alu", 281 fuType = FuType.alu, 282 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 283 srcData = Seq( 284 Seq(IntData(), IntData()), 285 ), 286 piped = true, 287 writeIntRf = true, 288 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 289 ) 290 291 val MulCfg: FuConfig = FuConfig ( 292 name = "mul", 293 fuType = FuType.mul, 294 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 295 srcData = Seq( 296 Seq(IntData(), IntData()), 297 ), 298 piped = true, 299 writeIntRf = true, 300 latency = CertainLatency(2), 301 ) 302 303 val DivCfg: FuConfig = FuConfig ( 304 name = "div", 305 fuType = FuType.div, 306 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 307 srcData = Seq( 308 Seq(IntData(), IntData()), 309 ), 310 piped = false, 311 writeIntRf = true, 312 latency = UncertainLatency(), 313 hasInputBuffer = (true, 4, true) 314 ) 315 316 val FenceCfg: FuConfig = FuConfig ( 317 name = "fence", 318 FuType.fence, 319 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 320 srcData = Seq( 321 Seq(IntData(), IntData()), 322 ), 323 piped = true, 324 latency = CertainLatency(0), 325 exceptionOut = Seq(illegalInstr), 326 flushPipe = true 327 ) 328 329 // Todo: split it to simple bitmap exu and complex bku 330 val BkuCfg: FuConfig = FuConfig ( 331 name = "bku", 332 fuType = FuType.bku, 333 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 334 srcData = Seq( 335 Seq(IntData(), IntData()), 336 ), 337 piped = true, 338 writeIntRf = true, 339 latency = CertainLatency(2), 340 ) 341 342 val VSetRvfWvfCfg: FuConfig = FuConfig( 343 name = "vsetrvfwvf", 344 fuType = FuType.vsetfwf, 345 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 346 srcData = Seq( 347 Seq(FpData(), FpData()), 348 ), 349 piped = true, 350 writeVecRf = true, 351 latency = CertainLatency(0), 352 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 353 ) 354 355 val VSetRiWvfCfg: FuConfig = FuConfig( 356 name = "vsetriwvf", 357 fuType = FuType.vsetiwf, 358 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 359 srcData = Seq( 360 Seq(IntData(), IntData()), 361 ), 362 piped = true, 363 writeVecRf = true, 364 latency = CertainLatency(0), 365 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 366 ) 367 368 val VSetRiWiCfg: FuConfig = FuConfig( 369 name = "vsetriwi", 370 fuType = FuType.vsetiwi, 371 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 372 srcData = Seq( 373 Seq(IntData(), IntData()), 374 ), 375 piped = true, 376 writeIntRf = true, 377 latency = CertainLatency(0), 378 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 379 ) 380 381 val FmacCfg: FuConfig = FuConfig ( 382 name = "fmac", 383 fuType = FuType.fmac, 384 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 385 srcData = Seq( 386 Seq(FpData(), FpData()), 387 Seq(FpData(), FpData(), FpData()), 388 ), 389 piped = false, 390 writeFpRf = true, 391 writeFflags = true, 392 latency = UncertainLatency(), 393 needSrcFrm = true, 394 ) 395 396 val F2iCfg: FuConfig = FuConfig ( 397 name = "f2i", 398 fuType = FuType.fmisc, 399 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 400 srcData = Seq( 401 Seq(FpData(), FpData()), 402 Seq(FpData()), 403 ), 404 piped = true, 405 writeIntRf = true, 406 writeFflags = true, 407 latency = CertainLatency(2), 408 needSrcFrm = true, 409 ) 410 411 val F2fCfg: FuConfig = FuConfig ( 412 name = "f2f", 413 fuType = FuType.fmisc, 414 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 415 srcData = Seq( 416 Seq(FpData(), FpData()), 417 Seq(FpData()), 418 ), 419 piped = true, 420 writeFpRf = true, 421 writeFflags = true, 422 latency = CertainLatency(2), 423 needSrcFrm = true, 424 ) 425 426 val FDivSqrtCfg: FuConfig = FuConfig ( 427 name = "fDivSqrt", 428 fuType = FuType.fDivSqrt, 429 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 430 srcData = Seq( 431 Seq(FpData(), FpData()), 432 ), 433 piped = false, 434 writeFpRf = true, 435 writeFflags = true, 436 latency = UncertainLatency(), 437 hasInputBuffer = (true, 8, true), 438 needSrcFrm = true, 439 ) 440 441 val LduCfg: FuConfig = FuConfig ( 442 name = "ldu", 443 fuType = FuType.ldu, 444 fuGen = null, // Todo 445 srcData = Seq( 446 Seq(IntData()), 447 ), 448 piped = false, // Todo: check it 449 writeIntRf = true, 450 writeFpRf = true, 451 latency = UncertainLatency(3), 452 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 453 flushPipe = true, 454 replayInst = true, 455 hasLoadError = true, 456 trigger = true, 457 immType = Set(SelImm.IMM_I), 458 ) 459 460 val StaCfg: FuConfig = FuConfig ( 461 name = "sta", 462 fuType = FuType.stu, 463 fuGen = null, // Todo 464 srcData = Seq( 465 Seq(IntData()), 466 ), 467 piped = false, 468 latency = UncertainLatency(), 469 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 470 trigger = true, 471 immType = Set(SelImm.IMM_S), 472 ) 473 474 val StdCfg: FuConfig = FuConfig ( 475 name = "std", 476 fuType = FuType.stu, 477 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 478 srcData = Seq( 479 Seq(IntData()), 480 Seq(FpData()), 481 ), 482 piped = true, 483 latency = CertainLatency(0) 484 ) 485 486 val HyldaCfg = FuConfig ( 487 name = "hylda", 488 fuType = FuType.ldu, 489 fuGen = null, // Todo 490 srcData = Seq( 491 Seq(IntData()), 492 ), 493 piped = false, // Todo: check it 494 writeIntRf = true, 495 writeFpRf = true, 496 latency = UncertainLatency(3), 497 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 498 flushPipe = true, 499 replayInst = true, 500 hasLoadError = true, 501 immType = Set(SelImm.IMM_I), 502 ) 503 504 val HystaCfg = FuConfig ( 505 name = "hysta", 506 fuType = FuType.stu, 507 fuGen = null, // Todo 508 srcData = Seq( 509 Seq(IntData()), 510 ), 511 piped = false, 512 latency = UncertainLatency(), 513 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 514 immType = Set(SelImm.IMM_S), 515 ) 516 517 val FakeHystaCfg = FuConfig ( 518 name = "hysta", 519 fuType = FuType.stu, 520 fuGen = null, // Todo 521 srcData = Seq(), 522 piped = false, 523 latency = UncertainLatency(), 524 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 525 immType = Set(), 526 ) 527 528 val MouCfg: FuConfig = FuConfig ( 529 name = "mou", 530 fuType = FuType.mou, 531 fuGen = null, // Todo 532 srcData = Seq( 533 Seq(IntData()), 534 ), 535 piped = false, // Todo: check it 536 writeFakeIntRf = true, 537 latency = UncertainLatency(), 538 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 539 trigger = true, 540 ) 541 542 val MoudCfg: FuConfig = FuConfig ( 543 name = "moud", 544 fuType = FuType.mou, 545 fuGen = null, // Todo 546 srcData = Seq( 547 Seq(IntData()), 548 ), 549 piped = true, 550 latency = CertainLatency(0), 551 ) 552 553 val VialuCfg = FuConfig ( 554 name = "vialuFix", 555 fuType = FuType.vialuF, 556 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 557 srcData = Seq( 558 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 559 ), 560 piped = true, 561 writeVecRf = true, 562 writeVxsat = true, 563 needSrcVxrm = true, 564 latency = CertainLatency(1), 565 vconfigWakeUp = true, 566 maskWakeUp = true, 567 dataBits = 128, 568 exceptionOut = Seq(illegalInstr), 569 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 570 ) 571 572 val VimacCfg = FuConfig ( 573 name = "vimac", 574 fuType = FuType.vimac, 575 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 576 srcData = Seq( 577 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 578 ), 579 piped = true, 580 writeVecRf = true, 581 writeVxsat = true, 582 needSrcVxrm = true, 583 latency = CertainLatency(2), 584 vconfigWakeUp = true, 585 maskWakeUp = true, 586 dataBits = 128, 587 exceptionOut = Seq(illegalInstr), 588 ) 589 590 val VidivCfg = FuConfig ( 591 name = "vidiv", 592 fuType = FuType.vidiv, 593 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 594 srcData = Seq( 595 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 596 ), 597 piped = false, 598 writeVecRf = true, 599 latency = UncertainLatency(), 600 vconfigWakeUp = true, 601 maskWakeUp = true, 602 dataBits = 128, 603 exceptionOut = Seq(illegalInstr), 604 ) 605 606 val VppuCfg = FuConfig ( 607 name = "vppu", 608 fuType = FuType.vppu, 609 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 610 srcData = Seq( 611 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 612 ), 613 piped = true, 614 writeVecRf = true, 615 latency = CertainLatency(1), 616 vconfigWakeUp = true, 617 maskWakeUp = true, 618 dataBits = 128, 619 exceptionOut = Seq(illegalInstr), 620 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 621 ) 622 623 val VipuCfg: FuConfig = FuConfig ( 624 name = "vipu", 625 fuType = FuType.vipu, 626 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 627 srcData = Seq( 628 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 629 ), 630 piped = true, 631 writeIntRf = true, 632 writeVecRf = true, 633 latency = CertainLatency(1), 634 vconfigWakeUp = true, 635 maskWakeUp = true, 636 dataBits = 128, 637 exceptionOut = Seq(illegalInstr), 638 ) 639 640 val VfaluCfg = FuConfig ( 641 name = "vfalu", 642 fuType = FuType.vfalu, 643 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 644 srcData = Seq( 645 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 646 ), 647 piped = true, 648 writeVecRf = true, 649 writeFpRf = true, 650 writeIntRf = true, 651 writeFflags = true, 652 latency = CertainLatency(1), 653 vconfigWakeUp = true, 654 maskWakeUp = true, 655 dataBits = 128, 656 exceptionOut = Seq(illegalInstr), 657 needSrcFrm = true, 658 ) 659 660 val VfmaCfg = FuConfig ( 661 name = "vfma", 662 fuType = FuType.vfma, 663 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 664 srcData = Seq( 665 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 666 ), 667 piped = true, 668 writeVecRf = true, 669 writeFpRf = true, 670 writeFflags = true, 671 latency = CertainLatency(3), 672 vconfigWakeUp = true, 673 maskWakeUp = true, 674 dataBits = 128, 675 exceptionOut = Seq(illegalInstr), 676 needSrcFrm = true, 677 ) 678 679 val VfdivCfg = FuConfig( 680 name = "vfdiv", 681 fuType = FuType.vfdiv, 682 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 683 srcData = Seq( 684 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 685 ), 686 piped = false, 687 writeVecRf = true, 688 writeFpRf = true, 689 writeFflags = true, 690 latency = UncertainLatency(), 691 vconfigWakeUp = true, 692 maskWakeUp = true, 693 dataBits = 128, 694 exceptionOut = Seq(illegalInstr), 695 needSrcFrm = true, 696 ) 697 698 val VfcvtCfg = FuConfig( 699 name = "vfcvt", 700 fuType = FuType.vfcvt, 701 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 702 srcData = Seq( 703 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 704 ), 705 piped = true, 706 writeVecRf = true, 707 writeFpRf = true, 708 writeIntRf = true, 709 writeFflags = true, 710 latency = CertainLatency(2), 711 vconfigWakeUp = true, 712 maskWakeUp = true, 713 dataBits = 128, 714 exceptionOut = Seq(illegalInstr), 715 needSrcFrm = true, 716 ) 717 718 719 val VlduCfg: FuConfig = FuConfig ( 720 name = "vldu", 721 fuType = FuType.vldu, 722 fuGen = null, 723 srcData = Seq( 724 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 725 ), 726 piped = false, // Todo: check it 727 writeVecRf = true, 728 latency = UncertainLatency(), 729 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 730 flushPipe = true, 731 replayInst = true, 732 hasLoadError = true, 733 vconfigWakeUp = true, 734 maskWakeUp = true, 735 dataBits = 128, 736 ) 737 738 val VstuCfg: FuConfig = FuConfig ( 739 name = "vstu", 740 fuType = FuType.vstu, 741 fuGen = null, 742 srcData = Seq( 743 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 744 ), 745 piped = false, 746 writeVecRf = false, 747 latency = UncertainLatency(), 748 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 749 flushPipe = true, 750 replayInst = true, 751 hasLoadError = true, 752 vconfigWakeUp = true, 753 maskWakeUp = true, 754 dataBits = 128, 755 ) 756 757 def allConfigs = Seq( 758 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 759 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 760 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 761 ) 762 763 def VecArithFuConfigs = Seq( 764 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 765 ) 766} 767 768