1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 32import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 33 34class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 35 val io = IO(new Bundle() { 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val stin = Flipped(Decoupled(new MemExuInput)) 38 val issue = Valid(new MemExuInput) 39 val tlb = new TlbRequestIO() 40 val dcache = new DCacheStoreIO 41 val pmp = Flipped(new PMPRespBundle()) 42 val lsq = ValidIO(new LsPipelineBundle) 43 val lsq_replenish = Output(new LsPipelineBundle()) 44 val feedback_slow = ValidIO(new RSFeedback) 45 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 46 // provide prefetch info to sms 47 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 48 val stld_nuke_query = Valid(new StoreNukeQueryIO) 49 val stout = DecoupledIO(new MemExuOutput) // writeback store 50 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 51 // store mask, send to sq in store_s0 52 val st_mask_out = Valid(new StoreMaskBundle) 53 val debug_ls = Output(new DebugLsInfoBundle) 54 // vector 55 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 56 val vec_isFirstIssue = Input(Bool()) 57 }) 58 59 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 60 61 // Pipeline 62 // -------------------------------------------------------------------------------- 63 // stage 0 64 // -------------------------------------------------------------------------------- 65 // generate addr, use addr to query DCache and DTLB 66 val s0_iss_valid = io.stin.valid 67 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 68 val s0_vec_valid = io.vecstin.valid 69 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid 70 val s0_use_flow_vec = s0_vec_valid 71 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid 72 val s0_use_flow_prf = !s0_iss_valid && !s0_vec_valid && s0_prf_valid 73 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 74 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 75 val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) 76 val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 77 val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) 78 val s0_size = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 79 val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) 80 val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 81 val s0_pc = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.pc, 0.U) 82 val s0_instr_type = Mux(s0_use_flow_rs || s0_use_flow_vec, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 83 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 84 val s0_out = Wire(new LsPipelineBundle) 85 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 86 val s0_can_go = s1_ready 87 val s0_fire = s0_valid && !s0_kill && s0_can_go 88 // vector 89 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 90 // val s0_flowPtr = s0_vecstin.flowPtr 91 // val s0_isLastElem = s0_vecstin.isLastElem 92 val s0_secondInv = s0_vecstin.usSecondInv 93 val s0_mBIndex = s0_vecstin.mBIndex 94 95 // generate addr 96 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.imm(11,0), VAddrBits) 97 val imm12 = WireInit(s0_uop.imm(11,0)) 98 val saddr_lo = s0_stin.src(0)(11,0) + Cat(0.U(1.W), imm12) 99 val saddr_hi = Mux(saddr_lo(12), 100 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12), s0_stin.src(0)(VAddrBits-1, 12)+1.U), 101 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_stin.src(0)(VAddrBits-1, 12)), 102 ) 103 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 104 val s0_vaddr = Mux( 105 s0_use_flow_rs, 106 s0_saddr, 107 Mux( 108 s0_use_flow_vec, 109 s0_vecstin.vaddr, 110 io.prefetch_req.bits.vaddr 111 ) 112 ) 113 val s0_mask = Mux( 114 s0_use_flow_rs, 115 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 116 Mux( 117 s0_use_flow_vec, 118 s0_vecstin.mask, 119 // -1.asSInt.asUInt 120 Fill(VLEN/8, 1.U(1.W)) 121 ) 122 ) 123 124 io.tlb.req.valid := s0_valid 125 io.tlb.req.bits.vaddr := s0_vaddr 126 io.tlb.req.bits.cmd := TlbCmd.write 127 io.tlb.req.bits.size := s0_size 128 io.tlb.req.bits.kill := false.B 129 io.tlb.req.bits.memidx.is_ld := false.B 130 io.tlb.req.bits.memidx.is_st := true.B 131 io.tlb.req.bits.memidx.idx := s0_mem_idx 132 io.tlb.req.bits.debug.robIdx := s0_rob_idx 133 io.tlb.req.bits.no_translate := false.B 134 io.tlb.req.bits.debug.pc := s0_pc 135 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 136 io.tlb.req_kill := false.B 137 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 138 io.tlb.req.bits.hlvx := false.B 139 140 // Dcache access here: not **real** dcache write 141 // just read meta and tag in dcache, to find out the store will hit or miss 142 143 // NOTE: The store request does not wait for the dcache to be ready. 144 // If the dcache is not ready at this time, the dcache is not queried. 145 // But, store prefetch request will always wait for dcache to be ready to make progress. 146 io.dcache.req.valid := s0_fire 147 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 148 io.dcache.req.bits.vaddr := s0_vaddr 149 io.dcache.req.bits.instrtype := s0_instr_type 150 151 s0_out := DontCare 152 s0_out.vaddr := s0_vaddr 153 // Now data use its own io 154 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 155 s0_out.data := s0_stin.src(1) 156 s0_out.uop := s0_uop 157 s0_out.miss := false.B 158 s0_out.rsIdx := s0_rsIdx 159 s0_out.mask := s0_mask 160 s0_out.isFirstIssue := s0_isFirstIssue 161 s0_out.isHWPrefetch := s0_use_flow_prf 162 s0_out.wlineflag := s0_wlineflag 163 s0_out.isvec := s0_use_flow_vec 164 s0_out.is128bit := false.B 165 s0_out.vecActive := s0_vecActive 166 s0_out.usSecondInv := s0_secondInv 167 s0_out.mbIndex := s0_mBIndex 168 when(s0_valid && s0_isFirstIssue) { 169 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 170 } 171 172 // exception check 173 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 174 "b00".U -> true.B, //b 175 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 176 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 177 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 178 )) 179 // if vector store sends 128-bit requests, its address must be 128-aligned 180 XSError(s0_use_flow_vec && s0_out.vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 181 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs || s0_use_flow_vec, !s0_addr_aligned, false.B) 182 183 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 184 io.st_mask_out.bits.mask := s0_out.mask 185 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 186 187 io.stin.ready := s1_ready && s0_use_flow_rs 188 io.vecstin.ready := s1_ready && s0_use_flow_vec 189 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid 190 191 // Pipeline 192 // -------------------------------------------------------------------------------- 193 // stage 1 194 // -------------------------------------------------------------------------------- 195 // TLB resp (send paddr to dcache) 196 val s1_valid = RegInit(false.B) 197 val s1_in = RegEnable(s0_out, s0_fire) 198 val s1_out = Wire(new LsPipelineBundle) 199 val s1_kill = Wire(Bool()) 200 val s1_can_go = s2_ready 201 val s1_fire = s1_valid && !s1_kill && s1_can_go 202 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 203 204 // mmio cbo decoder 205 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 206 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 207 s1_in.uop.fuOpType === LSUOpType.cbo_inval 208 val s1_paddr = io.tlb.resp.bits.paddr(0) 209 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 210 val s1_tlb_miss = io.tlb.resp.bits.miss 211 val s1_mmio = s1_mmio_cbo 212 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 213 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 214 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 215 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec) 216 217 s1_ready := !s1_valid || s1_kill || s2_ready 218 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 219 when (s0_fire) { s1_valid := true.B } 220 .elsewhen (s1_fire) { s1_valid := false.B } 221 .elsewhen (s1_kill) { s1_valid := false.B } 222 223 // st-ld violation dectect request. 224 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 225 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 226 io.stld_nuke_query.bits.paddr := s1_paddr 227 io.stld_nuke_query.bits.mask := s1_in.mask 228 229 // issue 230 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec 231 io.issue.bits := RegEnable(s0_stin, s0_valid) 232 233 234 // Send TLB feedback to store issue queue 235 // Store feedback is generated in store_s1, sent to RS in store_s2 236 val s1_feedback = Wire(Valid(new RSFeedback)) 237 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 238 s1_feedback.bits.hit := !s1_tlb_miss 239 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 240 s1_feedback.bits.robIdx := s1_out.uop.robIdx 241 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 242 s1_feedback.bits.dataInvalidSqIdx := DontCare 243 244 XSDebug(s1_feedback.valid, 245 "S1 Store: tlbHit: %d robIdx: %d\n", 246 s1_feedback.bits.hit, 247 s1_feedback.bits.robIdx.value 248 ) 249 250 // io.feedback_slow := s1_feedback 251 252 // get paddr from dtlb, check if rollback is needed 253 // writeback store inst to lsq 254 s1_out := s1_in 255 s1_out.paddr := s1_paddr 256 s1_out.gpaddr := s1_gpaddr 257 s1_out.miss := false.B 258 s1_out.mmio := s1_mmio 259 s1_out.tlbMiss := s1_tlb_miss 260 s1_out.atomic := s1_mmio 261 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 262 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 263 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 264 265 // scalar store and scalar load nuke check, and also other purposes 266 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 267 io.lsq.bits := s1_out 268 io.lsq.bits.miss := s1_tlb_miss 269 270 // kill dcache write intent request when tlb miss or exception 271 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 272 io.dcache.s1_paddr := s1_paddr 273 274 // write below io.out.bits assign sentence to prevent overwriting values 275 val s1_tlb_memidx = io.tlb.resp.bits.memidx 276 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 277 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 278 s1_out.uop.debugInfo.tlbRespTime := GTimer() 279 } 280 281 // Pipeline 282 // -------------------------------------------------------------------------------- 283 // stage 2 284 // -------------------------------------------------------------------------------- 285 // mmio check 286 val s2_valid = RegInit(false.B) 287 val s2_in = RegEnable(s1_out, s1_fire) 288 val s2_out = Wire(new LsPipelineBundle) 289 val s2_kill = Wire(Bool()) 290 val s2_can_go = s3_ready 291 val s2_fire = s2_valid && !s2_kill && s2_can_go 292 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 293 294 s2_ready := !s2_valid || s2_kill || s3_ready 295 when (s1_fire) { s2_valid := true.B } 296 .elsewhen (s2_fire) { s2_valid := false.B } 297 .elsewhen (s2_kill) { s2_valid := false.B } 298 299 val s2_pmp = WireInit(io.pmp) 300 301 val s2_exception = (ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) && RegNext(s1_feedback.bits.hit) 302 val s2_mmio = (s2_in.mmio || s2_pmp.mmio) && RegNext(s1_feedback.bits.hit) 303 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect) 304 305 s2_out := s2_in 306 s2_out.mmio := s2_mmio && !s2_exception 307 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 308 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st) && s2_vecActive 309 310 // kill dcache write intent request when mmio or exception 311 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 312 io.dcache.s2_pc := s2_out.uop.pc 313 // TODO: dcache resp 314 io.dcache.resp.ready := true.B 315 316 // feedback tlb miss to RS in store_s2 317 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) && !RegNext(s1_out.isvec) 318 io.feedback_slow.bits := RegNext(s1_feedback.bits) 319 320 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit) && s2_in.isvec 321 322 // mmio and exception 323 io.lsq_replenish := s2_out 324 325 // prefetch related 326 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 327 328 // RegNext prefetch train for better timing 329 // ** Now, prefetch train is valid at store s3 ** 330 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true) 331 // override miss bit 332 io.prefetch_train.bits.miss := RegNext(io.dcache.resp.bits.miss) 333 // TODO: add prefetch and access bit 334 io.prefetch_train.bits.meta_prefetch := false.B 335 io.prefetch_train.bits.meta_access := false.B 336 if(EnableStorePrefetchSMS) { 337 io.prefetch_train.valid := RegNext(s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch) 338 }else { 339 io.prefetch_train.valid := false.B 340 } 341 342 // Pipeline 343 // -------------------------------------------------------------------------------- 344 // stage 3 345 // -------------------------------------------------------------------------------- 346 // store write back 347 val s3_valid = RegInit(false.B) 348 val s3_in = RegEnable(s2_out, s2_fire) 349 val s3_out = Wire(new MemExuOutput(isVector = true)) 350 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 351 val s3_can_go = s3_ready 352 val s3_fire = s3_valid && !s3_kill && s3_can_go 353 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 354 355 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 356 .elsewhen (s3_fire) { s3_valid := false.B } 357 .elsewhen (s3_kill) { s3_valid := false.B } 358 359 // wb: writeback 360 val SelectGroupSize = RollbackGroupSize 361 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 362 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 363 364 s3_out := DontCare 365 s3_out.uop := s3_in.uop 366 s3_out.data := DontCare 367 s3_out.debug.isMMIO := s3_in.mmio 368 s3_out.debug.paddr := s3_in.paddr 369 s3_out.debug.vaddr := s3_in.vaddr 370 s3_out.debug.isPerfCnt := false.B 371 372 // Pipeline 373 // -------------------------------------------------------------------------------- 374 // stage x 375 // -------------------------------------------------------------------------------- 376 // delay TotalSelectCycles - 2 cycle(s) 377 val TotalDelayCycles = TotalSelectCycles - 2 378 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 379 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 380 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 381 382 // backward ready signal 383 s3_ready := sx_ready.head 384 for (i <- 0 until TotalDelayCycles + 1) { 385 if (i == 0) { 386 sx_valid(i) := s3_valid 387 sx_in(i).output := s3_out 388 sx_in(i).vecFeedback := s3_vecFeedback 389 sx_in(i).mmio := s3_in.mmio 390 sx_in(i).usSecondInv := s3_in.usSecondInv 391 sx_in(i).elemIdx := s3_in.elemIdx 392 sx_in(i).alignedType := s3_in.alignedType 393 sx_in(i).mbIndex := s3_in.mbIndex 394 sx_in(i).mask := s3_in.mask 395 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 396 } else { 397 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 398 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 399 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 400 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 401 402 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 403 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 404 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 405 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 406 } 407 } 408 val sx_last_valid = sx_valid.takeRight(1).head 409 val sx_last_ready = sx_ready.takeRight(1).head 410 val sx_last_in = sx_in.takeRight(1).head 411 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 412 413 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.output.uop.fuType) 414 io.stout.bits := sx_last_in.output 415 416 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isVStore(sx_last_in.output.uop.fuType) 417 // TODO: implement it! 418 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 419 io.vecstout.bits.hit := sx_last_in.vecFeedback 420 io.vecstout.bits.isvec := true.B 421 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 422 io.vecstout.bits.flushState := DontCare 423 io.vecstout.bits.mmio := sx_last_in.mmio 424 io.vecstout.bits.exceptionVec := sx_last_in.output.uop.exceptionVec 425 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 426 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 427 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 428 io.vecstout.bits.alignedType := sx_last_in.alignedType 429 io.vecstout.bits.mask := sx_last_in.mask 430 // io.vecstout.bits.reg_offset.map(_ := DontCare) 431 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 432 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 433 // io.vecstout.bits.vecdata.map(_ := DontCare) 434 // io.vecstout.bits.mask.map(_ := DontCare) 435 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 436 437 io.debug_ls := DontCare 438 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 439 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 440 441 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 442 XSDebug(cond, 443 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 444 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 445 p"op ${Binary(pipeline.uop.fuOpType)} " + 446 p"data ${Hexadecimal(pipeline.data)} " + 447 p"mask ${Hexadecimal(pipeline.mask)}\n" 448 ) 449 } 450 451 printPipeLine(s0_out, s0_valid, "S0") 452 printPipeLine(s1_out, s1_valid, "S1") 453 454 // perf cnt 455 XSPerfAccumulate("s0_in_valid", s0_valid) 456 XSPerfAccumulate("s0_in_fire", s0_fire) 457 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 458 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 459 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 460 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 461 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 462 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 463 464 XSPerfAccumulate("s1_in_valid", s1_valid) 465 XSPerfAccumulate("s1_in_fire", s1_fire) 466 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 467 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 468 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 469 // end 470}