1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.backend.fu._ 32import xiangshan.backend.fu.util.SdtrigExt 33import xiangshan.cache._ 34import xiangshan.cache.wpu.ReplayCarry 35import xiangshan.cache.mmu.{TlbCmd, TlbHintReq, TlbReq, TlbRequestIO, TlbResp} 36import xiangshan.mem.mdp._ 37 38class HybridUnit(implicit p: Parameters) extends XSModule 39 with HasLoadHelper 40 with HasPerfEvents 41 with HasDCacheParameters 42 with HasCircularQueuePtrHelper 43 with HasVLSUParameters 44 with SdtrigExt 45{ 46 val io = IO(new Bundle() { 47 // control 48 val redirect = Flipped(ValidIO(new Redirect)) 49 val csrCtrl = Flipped(new CustomCSRCtrlIO) 50 51 // flow in 52 val lsin = Flipped(Decoupled(new MemExuInput)) 53 54 // flow out 55 val ldout = DecoupledIO(new MemExuOutput) 56 val stout = DecoupledIO(new MemExuOutput) 57 58 val ldu_io = new Bundle() { 59 // dcache 60 val dcache = new DCacheLoadIO 61 62 // data path 63 val sbuffer = new LoadForwardQueryIO 64 val vec_forward = new LoadForwardQueryIO 65 val lsq = new LoadToLsqIO 66 val tl_d_channel = Input(new DcacheToLduForwardIO) 67 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 68 val tlb_hint = Flipped(new TlbHintReq) 69 val l2_hint = Input(Valid(new L2ToL1Hint)) 70 71 // fast wakeup 72 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 73 74 // trigger 75 val trigger = Vec(TriggerNum, new LoadUnitTriggerIO) 76 77 // load to load fast path 78 val l2l_fwd_in = Input(new LoadToLoadIO) 79 val l2l_fwd_out = Output(new LoadToLoadIO) 80 81 val ld_fast_match = Input(Bool()) 82 val ld_fast_fuOpType = Input(UInt()) 83 val ld_fast_imm = Input(UInt(12.W)) 84 85 // hardware prefetch to l1 cache req 86 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 87 88 // iq cancel 89 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 90 91 // iq wakeup, use to wakeup consumer uop at load s2 92 val wakeup = ValidIO(new DynInst) 93 94 // load ecc error 95 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 96 97 // schedule error query 98 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 99 100 // queue-based replay 101 val replay = Flipped(Decoupled(new LsPipelineBundle)) 102 val lq_rep_full = Input(Bool()) 103 104 // misc 105 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 106 107 // Load fast replay path 108 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 109 val fast_rep_out = Decoupled(new LqWriteBundle) 110 111 // Load RAR rollback 112 val rollback = Valid(new Redirect) 113 114 // perf 115 val debug_ls = Output(new DebugLsInfoBundle) 116 val lsTopdownInfo = Output(new LsTopdownInfo) 117 } 118 119 val stu_io = new Bundle() { 120 val dcache = new DCacheStoreIO 121 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 122 val issue = Valid(new MemExuInput) 123 val lsq = ValidIO(new LsPipelineBundle) 124 val lsq_replenish = Output(new LsPipelineBundle()) 125 val stld_nuke_query = Valid(new StoreNukeQueryIO) 126 val st_mask_out = Valid(new StoreMaskBundle) 127 val debug_ls = Output(new DebugLsInfoBundle) 128 } 129 130 val vec_stu_io = new Bundle() { 131 val in = Flipped(DecoupledIO(new VecPipeBundle())) 132 val isFirstIssue = Input(Bool()) 133 val lsq = ValidIO(new LsPipelineBundle()) 134 val feedbackSlow = ValidIO(new VSFQFeedback) 135 } 136 137 // speculative for gated control 138 val s0_prefetch_spec = Output(Bool()) 139 val s1_prefetch_spec = Output(Bool()) 140 // prefetch 141 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 142 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 143 val canAcceptLowConfPrefetch = Output(Bool()) 144 val canAcceptHighConfPrefetch = Output(Bool()) 145 val correctMissTrain = Input(Bool()) 146 147 // data path 148 val tlb = new TlbRequestIO(2) 149 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 150 151 // rs feedback 152 val feedback_fast = ValidIO(new RSFeedback) // stage 2 153 val feedback_slow = ValidIO(new RSFeedback) // stage 3 154 }) 155 156 val StorePrefetchL1Enabled = EnableStorePrefetchAtCommit || EnableStorePrefetchAtIssue || EnableStorePrefetchSPB 157 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 158 159 // Pipeline 160 // -------------------------------------------------------------------------------- 161 // stage 0 162 // -------------------------------------------------------------------------------- 163 // generate addr, use addr to query DCache and DTLB 164 val s0_valid = Wire(Bool()) 165 val s0_dcache_ready = Wire(Bool()) 166 val s0_kill = Wire(Bool()) 167 val s0_vaddr = Wire(UInt(VAddrBits.W)) 168 val s0_mask = Wire(UInt((VLEN/8).W)) 169 val s0_uop = Wire(new DynInst) 170 val s0_has_rob_entry = Wire(Bool()) 171 val s0_mshrid = Wire(UInt()) 172 val s0_try_l2l = Wire(Bool()) 173 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 174 val s0_isFirstIssue = Wire(Bool()) 175 val s0_fast_rep = Wire(Bool()) 176 val s0_ld_rep = Wire(Bool()) 177 val s0_l2l_fwd = Wire(Bool()) 178 val s0_sched_idx = Wire(UInt()) 179 val s0_can_go = s1_ready 180 val s0_fire = s0_valid && s0_dcache_ready && s0_can_go 181 val s0_out = Wire(new LqWriteBundle) 182 // vector 183 val s0_isvec = WireInit(false.B) 184 val s0_vecActive = WireInit(true.B) 185 // val s0_flowPtr = WireInit(0.U.asTypeOf(new VsFlowPtr)) 186 val s0_isLastElem = WireInit(false.B) 187 188 // load flow select/gen 189 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 190 // src1: fast load replay (io.ldu_io.fast_rep_in) 191 // src2: load replayed by LSQ (io.ldu_io.replay) 192 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 193 // src4: int read / software prefetch first issue from RS (io.in) 194 // src5: vec read first issue from RS (TODO) 195 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 196 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 197 // priority: high to low 198 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) || FuType.isVLoad(s0_uop.fuType) 199 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 200 val s0_super_ld_rep_valid = io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel 201 val s0_ld_fast_rep_valid = io.ldu_io.fast_rep_in.valid 202 val s0_ld_rep_valid = io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall 203 val s0_high_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U 204 val s0_int_iss_valid = io.lsin.valid // int flow first issue or software prefetch 205 val s0_vec_iss_valid = io.vec_stu_io.in.valid 206 val s0_l2l_fwd_valid = io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match 207 val s0_low_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U 208 dontTouch(s0_super_ld_rep_valid) 209 dontTouch(s0_ld_fast_rep_valid) 210 dontTouch(s0_ld_rep_valid) 211 dontTouch(s0_high_conf_prf_valid) 212 dontTouch(s0_int_iss_valid) 213 dontTouch(s0_vec_iss_valid) 214 dontTouch(s0_l2l_fwd_valid) 215 dontTouch(s0_low_conf_prf_valid) 216 217 // load flow source ready 218 val s0_super_ld_rep_ready = WireInit(true.B) 219 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 220 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 221 !s0_ld_fast_rep_valid 222 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 223 !s0_ld_fast_rep_valid && 224 !s0_ld_rep_valid 225 226 val s0_int_iss_ready = !s0_super_ld_rep_valid && 227 !s0_ld_fast_rep_valid && 228 !s0_ld_rep_valid && 229 !s0_high_conf_prf_valid 230 231 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 232 !s0_ld_fast_rep_valid && 233 !s0_ld_rep_valid && 234 !s0_high_conf_prf_valid && 235 !s0_int_iss_valid 236 237 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 238 !s0_ld_fast_rep_valid && 239 !s0_ld_rep_valid && 240 !s0_high_conf_prf_valid && 241 !s0_int_iss_valid && 242 !s0_vec_iss_valid 243 244 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 245 !s0_ld_fast_rep_valid && 246 !s0_ld_rep_valid && 247 !s0_high_conf_prf_valid && 248 !s0_int_iss_valid && 249 !s0_vec_iss_valid && 250 !s0_l2l_fwd_valid 251 dontTouch(s0_super_ld_rep_ready) 252 dontTouch(s0_ld_fast_rep_ready) 253 dontTouch(s0_ld_rep_ready) 254 dontTouch(s0_high_conf_prf_ready) 255 dontTouch(s0_int_iss_ready) 256 dontTouch(s0_vec_iss_ready) 257 dontTouch(s0_l2l_fwd_ready) 258 dontTouch(s0_low_conf_prf_ready) 259 260 // load flow source select (OH) 261 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 262 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 263 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 264 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 265 s0_low_conf_prf_ready && s0_low_conf_prf_valid 266 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 267 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 268 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 269 dontTouch(s0_super_ld_rep_select) 270 dontTouch(s0_ld_fast_rep_select) 271 dontTouch(s0_ld_rep_select) 272 dontTouch(s0_hw_prf_select) 273 dontTouch(s0_int_iss_select) 274 dontTouch(s0_vec_iss_select) 275 dontTouch(s0_l2l_fwd_select) 276 277 s0_valid := (s0_super_ld_rep_valid || 278 s0_ld_fast_rep_valid || 279 s0_ld_rep_valid || 280 s0_high_conf_prf_valid || 281 s0_int_iss_valid || 282 s0_vec_iss_valid || 283 s0_l2l_fwd_valid || 284 s0_low_conf_prf_valid) && !s0_kill 285 286 // which is S0's out is ready and dcache is ready 287 val s0_try_ptr_chasing = s0_l2l_fwd_select 288 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.ldu_io.dcache.req.ready 289 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 290 val s0_ptr_chasing_canceled = WireInit(false.B) 291 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 292 293 // prefetch related ctrl signal 294 val s0_prf = Wire(Bool()) 295 val s0_prf_rd = Wire(Bool()) 296 val s0_prf_wr = Wire(Bool()) 297 val s0_hw_prf = s0_hw_prf_select 298 299 io.canAcceptLowConfPrefetch := s0_low_conf_prf_ready && io.ldu_io.dcache.req.ready 300 io.canAcceptHighConfPrefetch := s0_high_conf_prf_ready && io.ldu_io.dcache.req.ready 301 302 if (StorePrefetchL1Enabled) { 303 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, io.stu_io.dcache.req.ready) 304 } else { 305 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, true.B) 306 } 307 308 // query DTLB 309 io.tlb.req.valid := s0_valid && s0_dcache_ready 310 io.tlb.req.bits.cmd := Mux(s0_prf, 311 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 312 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 313 ) 314 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 315 io.tlb.req.bits.size := Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1, 0), LSUOpType.size(s0_uop.fuOpType)) // may broken if use it in feature 316 io.tlb.req.bits.kill := s0_kill 317 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 318 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 319 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 320 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 321 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 322 io.tlb.req.bits.debug.pc := s0_uop.pc 323 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 324 325 // query DCache 326 // for load 327 io.ldu_io.dcache.req.valid := s0_valid && s0_dcache_ready && s0_ld_flow 328 io.ldu_io.dcache.req.bits.cmd := Mux(s0_prf_rd, MemoryOpConstants.M_PFR, 329 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD)) 330 io.ldu_io.dcache.req.bits.vaddr := s0_vaddr 331 io.ldu_io.dcache.req.bits.mask := s0_mask 332 io.ldu_io.dcache.req.bits.data := DontCare 333 io.ldu_io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 334 io.ldu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 335 io.ldu_io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 336 io.ldu_io.dcache.req.bits.replayCarry := s0_rep_carry 337 io.ldu_io.dcache.req.bits.id := DontCare // TODO: update cache meta 338 io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 339 io.ldu_io.dcache.is128Req := is128Bit(io.vec_stu_io.in.bits.alignedType) && io.vec_stu_io.in.valid && s0_vec_iss_select 340 341 // for store 342 io.stu_io.dcache.req.valid := s0_valid && s0_dcache_ready && !s0_ld_flow && !s0_prf 343 io.stu_io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 344 io.stu_io.dcache.req.bits.vaddr := s0_vaddr 345 io.stu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, STORE_SOURCE.U) 346 347 // load flow priority mux 348 def fromNullSource() = { 349 s0_vaddr := 0.U 350 s0_mask := 0.U 351 s0_uop := 0.U.asTypeOf(new DynInst) 352 s0_try_l2l := false.B 353 s0_has_rob_entry := false.B 354 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 355 s0_mshrid := 0.U 356 s0_isFirstIssue := false.B 357 s0_fast_rep := false.B 358 s0_ld_rep := false.B 359 s0_l2l_fwd := false.B 360 s0_prf := false.B 361 s0_prf_rd := false.B 362 s0_prf_wr := false.B 363 s0_sched_idx := 0.U 364 } 365 366 def fromFastReplaySource(src: LqWriteBundle) = { 367 s0_vaddr := src.vaddr 368 s0_mask := src.mask 369 s0_uop := src.uop 370 s0_try_l2l := false.B 371 s0_has_rob_entry := src.hasROBEntry 372 s0_rep_carry := src.rep_info.rep_carry 373 s0_mshrid := src.rep_info.mshr_id 374 s0_isFirstIssue := false.B 375 s0_fast_rep := true.B 376 s0_ld_rep := src.isLoadReplay 377 s0_l2l_fwd := false.B 378 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 379 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 380 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 381 s0_sched_idx := src.schedIndex 382 } 383 384 def fromNormalReplaySource(src: LsPipelineBundle) = { 385 s0_vaddr := src.vaddr 386 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 387 s0_uop := src.uop 388 s0_try_l2l := false.B 389 s0_has_rob_entry := true.B 390 s0_rep_carry := src.replayCarry 391 s0_mshrid := src.mshrid 392 s0_isFirstIssue := false.B 393 s0_fast_rep := false.B 394 s0_ld_rep := true.B 395 s0_l2l_fwd := false.B 396 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 397 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 398 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 399 s0_sched_idx := src.schedIndex 400 } 401 402 def fromPrefetchSource(src: L1PrefetchReq) = { 403 s0_vaddr := src.getVaddr() 404 s0_mask := 0.U 405 s0_uop := DontCare 406 s0_try_l2l := false.B 407 s0_has_rob_entry := false.B 408 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 409 s0_mshrid := 0.U 410 s0_isFirstIssue := false.B 411 s0_fast_rep := false.B 412 s0_ld_rep := false.B 413 s0_l2l_fwd := false.B 414 s0_prf := true.B 415 s0_prf_rd := !src.is_store 416 s0_prf_wr := src.is_store 417 s0_sched_idx := 0.U 418 } 419 420 def fromIntIssueSource(src: MemExuInput) = { 421 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 422 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 423 s0_uop := src.uop 424 s0_try_l2l := false.B 425 s0_has_rob_entry := true.B 426 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 427 s0_mshrid := 0.U 428 s0_isFirstIssue := true.B 429 s0_fast_rep := false.B 430 s0_ld_rep := false.B 431 s0_l2l_fwd := false.B 432 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 433 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 434 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 435 s0_sched_idx := 0.U 436 } 437 438 def fromVecIssueSource(src: VecPipeBundle) = { 439 // For now, vector port handles only vector store flows 440 s0_vaddr := src.vaddr 441 s0_mask := src.mask 442 s0_uop := src.uop 443 s0_try_l2l := false.B 444 s0_has_rob_entry := true.B 445 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 446 s0_mshrid := 0.U 447 // s0_isFirstIssue := src.isFirstIssue 448 s0_fast_rep := false.B 449 s0_ld_rep := false.B 450 s0_l2l_fwd := false.B 451 s0_prf := false.B 452 s0_prf_rd := false.B 453 s0_prf_wr := false.B 454 s0_sched_idx := 0.U 455 456 s0_isvec := true.B 457 s0_vecActive := io.vec_stu_io.in.bits.vecActive 458 // s0_flowPtr := io.vec_stu_io.in.bits.flowPtr 459 // s0_isLastElem := io.vec_stu_io.in.bits.isLastElem 460 } 461 462 def fromLoadToLoadSource(src: LoadToLoadIO) = { 463 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 464 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 465 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 466 // Assume the pointer chasing is always ld. 467 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 468 s0_try_l2l := true.B 469 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 470 // because these signals will be updated in S1 471 s0_has_rob_entry := false.B 472 s0_mshrid := 0.U 473 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 474 s0_isFirstIssue := true.B 475 s0_fast_rep := false.B 476 s0_ld_rep := false.B 477 s0_l2l_fwd := true.B 478 s0_prf := false.B 479 s0_prf_rd := false.B 480 s0_prf_wr := false.B 481 s0_sched_idx := 0.U 482 } 483 484 // set default 485 s0_uop := DontCare 486 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 487 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 488 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 489 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 490 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.lsin.bits) } 491 .elsewhen (s0_vec_iss_select) { fromVecIssueSource(io.vec_stu_io.in.bits) } 492 .otherwise { 493 if (EnableLoadToLoadForward) { 494 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 495 } else { 496 fromNullSource() 497 } 498 } 499 500 // address align check 501 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 502 "b00".U -> true.B, //b 503 "b01".U -> (s0_vaddr(0) === 0.U), //h 504 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 505 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 506 ))// may broken if use it in feature 507 508 // accept load flow if dcache ready (tlb is always ready) 509 // TODO: prefetch need writeback to loadQueueFlag 510 s0_out := DontCare 511 s0_out.vaddr := s0_vaddr 512 s0_out.mask := s0_mask 513 s0_out.uop := s0_uop 514 s0_out.isFirstIssue := s0_isFirstIssue 515 s0_out.hasROBEntry := s0_has_rob_entry 516 s0_out.isPrefetch := s0_prf 517 s0_out.isHWPrefetch := s0_hw_prf 518 s0_out.isFastReplay := s0_fast_rep 519 s0_out.isLoadReplay := s0_ld_rep 520 s0_out.isFastPath := s0_l2l_fwd 521 s0_out.mshrid := s0_mshrid 522 s0_out.isvec := s0_isvec 523 s0_out.isLastElem := s0_isLastElem 524 s0_out.vecActive := s0_vecActive 525 // s0_out.sflowPtr := s0_flowPtr 526 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 527 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 528 s0_out.forward_tlDchannel := s0_super_ld_rep_select 529 when(io.tlb.req.valid && s0_isFirstIssue) { 530 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 531 }.otherwise{ 532 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 533 } 534 s0_out.schedIndex := s0_sched_idx 535 536 // load fast replay 537 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.ldu_io.dcache.req.ready && s0_ld_fast_rep_ready) 538 539 // load flow source ready 540 // cache missed load has highest priority 541 // always accept cache missed load flow from load replay queue 542 io.ldu_io.replay.ready := (s0_can_go && io.ldu_io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 543 544 // accept load flow from rs when: 545 // 1) there is no lsq-replayed load 546 // 2) there is no fast replayed load 547 // 3) there is no high confidence prefetch request 548 io.lsin.ready := (s0_can_go && 549 Mux(FuType.isLoad(io.lsin.bits.uop.fuType), io.ldu_io.dcache.req.ready, 550 (if (StorePrefetchL1Enabled) io.stu_io.dcache.req.ready else true.B)) && s0_int_iss_ready) 551 io.vec_stu_io.in.ready := s0_can_go && io.ldu_io.dcache.req.ready && s0_vec_iss_ready 552 553 554 // for hw prefetch load flow feedback, to be added later 555 // io.prefetch_in.ready := s0_hw_prf_select 556 557 // dcache replacement extra info 558 // TODO: should prefetch load update replacement? 559 io.ldu_io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.ldu_io.replay.bits.replacementUpdated, false.B) 560 561 io.stu_io.prefetch_req.ready := s1_ready && io.stu_io.dcache.req.ready && !io.lsin.valid 562 563 // load debug 564 XSDebug(io.ldu_io.dcache.req.fire && s0_ld_flow, 565 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 566 ) 567 XSDebug(s0_valid && s0_ld_flow, 568 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 569 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 570 571 // store debug 572 XSDebug(io.stu_io.dcache.req.fire && !s0_ld_flow, 573 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 574 ) 575 XSDebug(s0_valid && !s0_ld_flow, 576 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 577 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 578 579 580 // Pipeline 581 // -------------------------------------------------------------------------------- 582 // stage 1 583 // -------------------------------------------------------------------------------- 584 // TLB resp (send paddr to dcache) 585 val s1_valid = RegInit(false.B) 586 val s1_in = Wire(new LqWriteBundle) 587 val s1_out = Wire(new LqWriteBundle) 588 val s1_kill = Wire(Bool()) 589 val s1_can_go = s2_ready 590 val s1_fire = s1_valid && !s1_kill && s1_can_go 591 val s1_ld_flow = RegNext(s0_ld_flow) 592 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 593 val s1_isLastElem = RegEnable(s0_out.isLastElem, false.B, s0_fire) 594 595 s1_ready := !s1_valid || s1_kill || s2_ready 596 when (s0_fire) { s1_valid := true.B } 597 .elsewhen (s1_fire) { s1_valid := false.B } 598 .elsewhen (s1_kill) { s1_valid := false.B } 599 s1_in := RegEnable(s0_out, s0_fire) 600 601 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 602 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 603 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 604 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 605 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 606 val s1_vaddr_hi = Wire(UInt()) 607 val s1_vaddr_lo = Wire(UInt()) 608 val s1_vaddr = Wire(UInt()) 609 val s1_paddr_dup_lsu = Wire(UInt()) 610 val s1_paddr_dup_dcache = Wire(UInt()) 611 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 612 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 613 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 614 val s1_tlb_miss = io.tlb.resp.bits.miss 615 val s1_prf = s1_in.isPrefetch 616 val s1_hw_prf = s1_in.isHWPrefetch 617 val s1_sw_prf = s1_prf && !s1_hw_prf 618 val s1_tlb_memidx = io.tlb.resp.bits.memidx 619 620 // mmio cbo decoder 621 val s1_mmio_cbo = (s1_in.uop.fuOpType === LSUOpType.cbo_clean || 622 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 623 s1_in.uop.fuOpType === LSUOpType.cbo_inval) && !s1_ld_flow && !s1_prf 624 val s1_mmio = s1_mmio_cbo 625 626 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 627 s1_vaddr_lo := s1_in.vaddr(5, 0) 628 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 629 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 630 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 631 632 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 633 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 634 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 635 s1_out.uop.debugInfo.tlbRespTime := GTimer() 636 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 637 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 638 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 639 s1_out.uop.debugInfo.tlbRespTime := GTimer() 640 } 641 642 io.tlb.req_kill := s1_kill 643 io.tlb.resp.ready := true.B 644 645 io.ldu_io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 646 io.ldu_io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 647 io.ldu_io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 648 649 // store to load forwarding 650 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 651 io.ldu_io.sbuffer.vaddr := s1_vaddr 652 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 653 io.ldu_io.sbuffer.uop := s1_in.uop 654 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 655 io.ldu_io.sbuffer.mask := s1_in.mask 656 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 657 658 io.ldu_io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 659 io.ldu_io.vec_forward.vaddr := s1_vaddr 660 io.ldu_io.vec_forward.paddr := s1_paddr_dup_lsu 661 io.ldu_io.vec_forward.uop := s1_in.uop 662 io.ldu_io.vec_forward.sqIdx := s1_in.uop.sqIdx 663 io.ldu_io.vec_forward.mask := s1_in.mask 664 io.ldu_io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 665 666 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 667 io.ldu_io.lsq.forward.vaddr := s1_vaddr 668 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 669 io.ldu_io.lsq.forward.uop := s1_in.uop 670 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 671 io.ldu_io.lsq.forward.sqIdxMask := 0.U 672 io.ldu_io.lsq.forward.mask := s1_in.mask 673 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 674 675 // st-ld violation query 676 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 677 io.ldu_io.stld_nuke_query(w).valid && // query valid 678 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 679 // TODO: Fix me when vector instruction 680 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 681 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 682 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 683 684 s1_out := s1_in 685 s1_out.vaddr := s1_vaddr 686 s1_out.paddr := s1_paddr_dup_lsu 687 s1_out.tlbMiss := s1_tlb_miss 688 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 689 s1_out.rep_info.debug := s1_in.uop.debugInfo 690 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 691 s1_out.lateKill := s1_late_kill 692 693 when (s1_ld_flow) { 694 when (!s1_late_kill) { 695 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 696 // af & pf exception were modified 697 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 698 s1_out.uop.exceptionVec(loadGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.ld 699 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 700 } .otherwise { 701 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 702 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 703 } 704 } .otherwise { 705 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 706 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st 707 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 708 } 709 710 // pointer chasing 711 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 712 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 713 val s1_fu_op_type_not_ld = WireInit(false.B) 714 val s1_not_fast_match = WireInit(false.B) 715 val s1_addr_mismatch = WireInit(false.B) 716 val s1_addr_misaligned = WireInit(false.B) 717 val s1_ptr_chasing_canceled = WireInit(false.B) 718 val s1_cancel_ptr_chasing = WireInit(false.B) 719 720 s1_kill := s1_late_kill || 721 s1_cancel_ptr_chasing || 722 s1_in.uop.robIdx.needFlush(io.redirect) || 723 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid || io.vec_stu_io.in.valid) 724 725 if (EnableLoadToLoadForward) { 726 // Sometimes, we need to cancel the load-load forwarding. 727 // These can be put at S0 if timing is bad at S1. 728 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 729 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 730 // Case 1: the address is misaligned, kill s1 731 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 732 "b00".U -> false.B, //b 733 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 734 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 735 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 736 )) 737 // Case 2: this load-load uop is cancelled 738 s1_ptr_chasing_canceled := !io.lsin.valid || FuType.isStore(io.lsin.bits.uop.fuType) 739 740 when (s1_try_ptr_chasing) { 741 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 742 743 s1_in.uop := io.lsin.bits.uop 744 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 745 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 746 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 747 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 748 749 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 750 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 751 s1_in.uop.debugInfo.tlbRespTime := GTimer() 752 } 753 when (!s1_cancel_ptr_chasing) { 754 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire && !(s0_high_conf_prf_valid && io.canAcceptHighConfPrefetch) 755 when (s1_try_ptr_chasing) { 756 io.lsin.ready := true.B 757 } 758 } 759 } 760 761 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 762 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 763 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 764 // If the timing here is not OK, load-load forwarding has to be disabled. 765 // Or we calculate sqIdxMask at RS?? 766 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 767 if (EnableLoadToLoadForward) { 768 when (s1_try_ptr_chasing) { 769 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 770 } 771 } 772 773 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 774 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 775 io.ldu_io.forward_mshr.paddr := s1_out.paddr 776 777 io.ldu_io.wakeup.valid := s0_fire && s0_ld_flow && (s0_super_ld_rep_select || s0_ld_fast_rep_select || s0_ld_rep_select || s0_int_iss_select) 778 io.ldu_io.wakeup.bits := s0_uop 779 780 io.stu_io.dcache.s1_kill := s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect) 781 io.stu_io.dcache.s1_paddr := s1_paddr_dup_dcache 782 783 784 // load debug 785 XSDebug(s1_valid && s1_ld_flow, 786 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 787 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 788 789 // store debug 790 XSDebug(s1_valid && !s1_ld_flow, 791 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 792 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 793 794 // store out 795 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && !s1_isvec 796 io.stu_io.lsq.bits := s1_out 797 io.stu_io.lsq.bits.miss := s1_tlb_miss 798 799 io.vec_stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && s1_isvec 800 io.vec_stu_io.lsq.bits := s1_out 801 io.vec_stu_io.lsq.bits.miss := s1_tlb_miss 802 io.vec_stu_io.lsq.bits.isLastElem := s1_isLastElem 803 804 io.stu_io.st_mask_out.valid := s1_valid && !s1_ld_flow && !s1_prf 805 io.stu_io.st_mask_out.bits.mask := s1_out.mask 806 io.stu_io.st_mask_out.bits.sqIdx := s1_out.uop.sqIdx 807 808 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf && !s1_isvec 809 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 810 811 // st-ld violation dectect request 812 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf 813 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 814 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 815 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 816 817 // Pipeline 818 // -------------------------------------------------------------------------------- 819 // stage 2 820 // -------------------------------------------------------------------------------- 821 // s2: DCache resp 822 val s2_valid = RegInit(false.B) 823 val s2_in = Wire(new LqWriteBundle) 824 val s2_out = Wire(new LqWriteBundle) 825 val s2_kill = Wire(Bool()) 826 val s2_can_go = s3_ready 827 val s2_fire = s2_valid && !s2_kill && s2_can_go 828 val s2_isvec = RegEnable(s1_isvec, false.B, s1_fire) 829 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 830 val s2_paddr = RegEnable(s1_paddr_dup_lsu, s1_fire) 831 832 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 833 s2_ready := !s2_valid || s2_kill || s3_ready 834 when (s1_fire) { s2_valid := true.B } 835 .elsewhen (s2_fire) { s2_valid := false.B } 836 .elsewhen (s2_kill) { s2_valid := false.B } 837 s2_in := RegEnable(s1_out, s1_fire) 838 839 val s2_pmp = WireInit(io.pmp) 840 841 val s2_prf = s2_in.isPrefetch 842 val s2_hw_prf = s2_in.isHWPrefetch 843 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 844 845 // exception that may cause load addr to be invalid / illegal 846 // if such exception happen, that inst and its exception info 847 // will be force writebacked to rob 848 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 849 when (s2_ld_flow) { 850 when (!s2_in.lateKill) { 851 s2_exception_vec(loadAccessFault) := (s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld) && s2_vecActive 852 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 853 when (s2_prf || s2_in.tlbMiss) { 854 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 855 } 856 } 857 } .otherwise { 858 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 859 when (s2_prf || s2_in.tlbMiss) { 860 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 861 } 862 } 863 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 864 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 865 val s2_exception = s2_ld_exception || s2_st_exception 866 867 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 868 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.ldu_io.forward_mshr.forward() 869 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 870 871 // writeback access fault caused by ecc error / bus error 872 // * ecc data error is slow to generate, so we will not use it until load stage 3 873 // * in load stage 3, an extra signal io.load_error will be used to 874 val s2_actually_mmio = s2_pmp.mmio 875 val s2_ld_mmio = !s2_prf && 876 s2_actually_mmio && 877 !s2_exception && 878 !s2_in.tlbMiss && 879 s2_ld_flow 880 val s2_st_mmio = !s2_prf && 881 (RegNext(s1_mmio) || s2_pmp.mmio) && 882 !s2_exception && 883 !s2_in.tlbMiss && 884 !s2_ld_flow 885 val s2_st_atomic = !s2_prf && 886 (RegNext(s1_mmio) || s2_pmp.atomic) && 887 !s2_exception && 888 !s2_in.tlbMiss && 889 !s2_ld_flow 890 val s2_full_fwd = Wire(Bool()) 891 val s2_mem_amb = s2_in.uop.storeSetHit && 892 io.ldu_io.lsq.forward.addrInvalid 893 894 val s2_tlb_miss = s2_in.tlbMiss 895 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid || io.ldu_io.vec_forward.dataInvalid 896 val s2_dcache_miss = io.ldu_io.dcache.resp.bits.miss && 897 !s2_fwd_frm_d_chan_or_mshr && 898 !s2_full_fwd 899 900 val s2_mq_nack = io.ldu_io.dcache.s2_mq_nack && 901 !s2_fwd_frm_d_chan_or_mshr && 902 !s2_full_fwd 903 904 val s2_bank_conflict = io.ldu_io.dcache.s2_bank_conflict && 905 !s2_fwd_frm_d_chan_or_mshr && 906 !s2_full_fwd 907 908 val s2_wpu_pred_fail = io.ldu_io.dcache.s2_wpu_pred_fail && 909 !s2_fwd_frm_d_chan_or_mshr && 910 !s2_full_fwd 911 912 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 913 !io.ldu_io.lsq.ldld_nuke_query.req.ready 914 915 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 916 !io.ldu_io.lsq.stld_nuke_query.req.ready 917 918 // st-ld violation query 919 // NeedFastRecovery Valid when 920 // 1. Fast recovery query request Valid. 921 // 2. Load instruction is younger than requestors(store instructions). 922 // 3. Physical address match. 923 // 4. Data contains. 924 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 925 io.ldu_io.stld_nuke_query(w).valid && // query valid 926 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 927 // TODO: Fix me when vector instruction 928 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 929 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 930 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 931 932 val s2_cache_handled = io.ldu_io.dcache.resp.bits.handled 933 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 934 io.ldu_io.dcache.resp.bits.tag_error 935 936 val s2_troublem = !s2_exception && 937 !s2_ld_mmio && 938 !s2_prf && 939 !s2_in.lateKill && 940 s2_ld_flow 941 942 io.ldu_io.dcache.resp.ready := true.B 943 io.stu_io.dcache.resp.ready := true.B 944 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_ld_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 945 assert(!(s2_valid && (s2_dcache_should_resp && !io.ldu_io.dcache.resp.valid)), "DCache response got lost") 946 947 // fast replay require 948 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 949 val s2_nuke_fast_rep = !s2_mq_nack && 950 !s2_dcache_miss && 951 !s2_bank_conflict && 952 !s2_wpu_pred_fail && 953 !s2_rar_nack && 954 !s2_raw_nack && 955 s2_nuke 956 957 val s2_fast_rep = !s2_mem_amb && 958 !s2_tlb_miss && 959 !s2_fwd_fail && 960 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 961 s2_troublem 962 963 // need allocate new entry 964 val s2_can_query = !s2_mem_amb && 965 !s2_tlb_miss && 966 !s2_fwd_fail && 967 !s2_dcache_fast_rep && 968 s2_troublem 969 970 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 971 972 // ld-ld violation require 973 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 974 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 975 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 976 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 977 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 978 979 // st-ld violation require 980 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 981 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 982 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 983 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 984 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 985 986 // merge forward result 987 // lsq has higher priority than sbuffer 988 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 989 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 990 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid && !io.ldu_io.vec_forward.dataInvalid 991 // generate XLEN/8 Muxs 992 for (i <- 0 until VLEN / 8) { 993 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) || io.ldu_io.vec_forward.forwardMask(i) 994 s2_fwd_data(i) := Mux( 995 io.ldu_io.lsq.forward.forwardMask(i), 996 io.ldu_io.lsq.forward.forwardData(i), 997 Mux( 998 io.ldu_io.vec_forward.forwardMask(i), 999 io.ldu_io.vec_forward.forwardData(i), 1000 io.ldu_io.sbuffer.forwardData(i) 1001 ) 1002 ) 1003 } 1004 1005 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 1006 s2_in.uop.pc, 1007 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 1008 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 1009 ) 1010 1011 // 1012 s2_out := s2_in 1013 s2_out.data := 0.U // data will be generated in load s3 1014 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 1015 s2_out.mmio := s2_ld_mmio || s2_st_mmio 1016 s2_out.atomic := s2_st_atomic 1017 s2_out.uop.flushPipe := false.B 1018 s2_out.uop.exceptionVec := s2_exception_vec 1019 s2_out.forwardMask := s2_fwd_mask 1020 s2_out.forwardData := s2_fwd_data 1021 s2_out.handledByMSHR := s2_cache_handled 1022 s2_out.miss := s2_dcache_miss && s2_troublem 1023 s2_out.feedbacked := io.feedback_fast.valid && !io.feedback_fast.bits.hit 1024 1025 // Generate replay signal caused by: 1026 // * st-ld violation check 1027 // * tlb miss 1028 // * dcache replay 1029 // * forward data invalid 1030 // * dcache miss 1031 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 1032 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 1033 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 1034 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 1035 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 1036 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 1037 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 1038 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 1039 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 1040 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1041 s2_out.rep_info.full_fwd := s2_data_fwded 1042 s2_out.rep_info.data_inv_sq_idx := Mux(io.ldu_io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.dataInvalidSqIdx) 1043 s2_out.rep_info.addr_inv_sq_idx := Mux(io.ldu_io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.addrInvalidSqIdx) 1044 s2_out.rep_info.rep_carry := io.ldu_io.dcache.resp.bits.replayCarry 1045 s2_out.rep_info.mshr_id := io.ldu_io.dcache.resp.bits.mshr_id 1046 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1047 s2_out.rep_info.debug := s2_in.uop.debugInfo 1048 s2_out.rep_info.tlb_id := io.ldu_io.tlb_hint.id 1049 s2_out.rep_info.tlb_full := io.ldu_io.tlb_hint.full 1050 1051 // if forward fail, replay this inst from fetch 1052 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1053 // if ld-ld violation is detected, replay from this inst from fetch 1054 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_ld_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1055 // io.out.bits.uop.replayInst := false.B 1056 1057 // to be removed 1058 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 1059 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 1060 s2_out.rep_info.need_rep && // need replay 1061 !s2_exception && // no exception is triggered 1062 !s2_hw_prf && // not hardware prefetch 1063 !s2_isvec 1064 val s2_st_need_fb = !s2_ld_flow && !s2_hw_prf && !s2_isvec 1065 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 1066 io.feedback_fast.bits.hit := Mux(s2_ld_flow, false.B, !s2_tlb_miss) 1067 io.feedback_fast.bits.flushState := s2_in.ptwBack 1068 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1069 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 1070 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1071 1072 val s2_vec_feedback = Wire(Valid(new VSFQFeedback)) 1073 s2_vec_feedback.valid := s2_valid && !s2_ld_flow && !s2_hw_prf && s2_isvec 1074 // s2_vec_feedback.bits.flowPtr := s2_out.sflowPtr 1075 s2_vec_feedback.bits.hit := !s2_tlb_miss 1076 s2_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 1077 s2_vec_feedback.bits.paddr := s2_paddr 1078 s2_vec_feedback.bits.mmio := s2_st_mmio 1079 s2_vec_feedback.bits.atomic := s2_st_mmio 1080 s2_vec_feedback.bits.exceptionVec := s2_exception_vec 1081 1082 io.stu_io.lsq_replenish := s2_out 1083 io.stu_io.lsq_replenish.miss := io.ldu_io.dcache.resp.fire && io.ldu_io.dcache.resp.bits.miss 1084 1085 io.ldu_io.ldCancel.ld1Cancel := false.B 1086 1087 // fast wakeup 1088 io.ldu_io.fast_uop.valid := RegNext( 1089 !io.ldu_io.dcache.s1_disable_fast_wakeup && 1090 s1_valid && 1091 !s1_kill && 1092 !io.tlb.resp.bits.miss && 1093 !io.ldu_io.lsq.forward.dataInvalidFast 1094 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_ld_mmio && s2_ld_flow) && !s2_isvec 1095 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 1096 1097 // 1098 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1099 1100 // prefetch train 1101 io.s0_prefetch_spec := s0_fire 1102 io.s1_prefetch_spec := s1_fire 1103 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1104 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1105 io.prefetch_train.bits.miss := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.miss, io.stu_io.dcache.resp.bits.miss) // TODO: use trace with bank conflict? 1106 io.prefetch_train.bits.meta_prefetch := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_prefetch, false.B) 1107 io.prefetch_train.bits.meta_access := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_access, false.B) 1108 1109 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio && s2_ld_flow 1110 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1111 io.prefetch_train_l1.bits.miss := io.ldu_io.dcache.resp.bits.miss 1112 io.prefetch_train_l1.bits.meta_prefetch := io.ldu_io.dcache.resp.bits.meta_prefetch 1113 io.prefetch_train_l1.bits.meta_access := io.ldu_io.dcache.resp.bits.meta_access 1114 if (env.FPGAPlatform){ 1115 io.ldu_io.dcache.s0_pc := DontCare 1116 io.ldu_io.dcache.s1_pc := DontCare 1117 io.ldu_io.dcache.s2_pc := DontCare 1118 }else{ 1119 io.ldu_io.dcache.s0_pc := s0_out.uop.pc 1120 io.ldu_io.dcache.s1_pc := s1_out.uop.pc 1121 io.ldu_io.dcache.s2_pc := s2_out.uop.pc 1122 } 1123 io.ldu_io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1124 io.stu_io.dcache.s2_kill := s2_pmp.st || s2_actually_mmio || s2_kill 1125 io.stu_io.dcache.s2_pc := s2_out.uop.pc 1126 1127 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1128 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1129 s2_ld_valid_dup := 0x0.U(6.W) 1130 when (s1_ld_left_fire && !s1_out.isHWPrefetch && s1_ld_flow) { s2_ld_valid_dup := 0x3f.U(6.W) } 1131 when (s1_kill || s1_out.isHWPrefetch || !s1_ld_flow) { s2_ld_valid_dup := 0x0.U(6.W) } 1132 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch) || RegNext(!s1_ld_flow))) 1133 1134 // Pipeline 1135 // -------------------------------------------------------------------------------- 1136 // stage 3 1137 // -------------------------------------------------------------------------------- 1138 // writeback and update load queue 1139 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1140 val s3_in = RegEnable(s2_out, s2_fire) 1141 val s3_out = Wire(Valid(new MemExuOutput)) 1142 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1143 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1144 val s3_fast_rep = Wire(Bool()) 1145 val s3_ld_flow = RegNext(s2_ld_flow) 1146 val s3_troublem = RegNext(s2_troublem) 1147 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1148 val s3_isvec = RegNext(s2_isvec) 1149 s3_ready := !s3_valid || s3_kill || sx_can_go 1150 1151 // forwrad last beat 1152 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 1153 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1154 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) && s3_ld_flow 1155 1156 1157 // s3 load fast replay 1158 io.ldu_io.fast_rep_out.valid := s3_valid && 1159 s3_fast_rep && 1160 !s3_in.uop.robIdx.needFlush(io.redirect) && 1161 s3_ld_flow && 1162 !s3_isvec 1163 io.ldu_io.fast_rep_out.bits := s3_in 1164 1165 io.ldu_io.lsq.ldin.valid := s3_valid && 1166 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1167 !s3_in.feedbacked && 1168 !s3_in.lateKill && 1169 s3_ld_flow 1170 io.ldu_io.lsq.ldin.bits := s3_in 1171 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1172 1173 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1174 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1175 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.ldu_io.dcache.resp.bits.replacementUpdated 1176 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1177 1178 val s3_dly_ld_err = 1179 if (EnableAccurateLoadError) { 1180 (s3_in.lateKill || io.ldu_io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1181 } else { 1182 WireInit(false.B) 1183 } 1184 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1185 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1186 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1187 1188 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid) && s3_troublem 1189 val s3_ldld_rep_inst = 1190 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1191 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1192 RegNext(io.csrCtrl.ldld_vio_check_enable) 1193 1194 val s3_rep_info = WireInit(s3_in.rep_info) 1195 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1196 val s3_rep_frm_fetch = s3_vp_match_fail 1197 val s3_flushPipe = s3_ldld_rep_inst 1198 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1199 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1200 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1201 s3_troublem 1202 1203 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1204 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1205 val s3_exception = s3_ld_exception || s3_st_exception 1206 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1207 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1208 } .otherwise { 1209 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1210 } 1211 1212 // Int flow, if hit, will be writebacked at s3 1213 s3_out.valid := s3_valid && 1214 (!s3_ld_flow && !s3_in.feedbacked || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep) && !s3_in.mmio 1215 s3_out.bits.uop := s3_in.uop 1216 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1217 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1218 s3_out.bits.data := s3_in.data 1219 s3_out.bits.debug.isMMIO := s3_in.mmio 1220 s3_out.bits.debug.isPerfCnt := false.B 1221 s3_out.bits.debug.paddr := s3_in.paddr 1222 s3_out.bits.debug.vaddr := s3_in.vaddr 1223 1224 when (s3_force_rep) { 1225 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1226 } 1227 1228 io.ldu_io.rollback.valid := s3_valid && (s3_rep_frm_fetch || s3_flushPipe) && !s3_exception && s3_ld_flow 1229 io.ldu_io.rollback.bits := DontCare 1230 io.ldu_io.rollback.bits.isRVC := s3_out.bits.uop.preDecodeInfo.isRVC 1231 io.ldu_io.rollback.bits.robIdx := s3_out.bits.uop.robIdx 1232 io.ldu_io.rollback.bits.ftqIdx := s3_out.bits.uop.ftqPtr 1233 io.ldu_io.rollback.bits.ftqOffset := s3_out.bits.uop.ftqOffset 1234 io.ldu_io.rollback.bits.level := Mux(s3_rep_frm_fetch, RedirectLevel.flush, RedirectLevel.flushAfter) 1235 io.ldu_io.rollback.bits.cfiUpdate.target := s3_out.bits.uop.pc 1236 io.ldu_io.rollback.bits.debug_runahead_checkpoint_id := s3_out.bits.uop.debugInfo.runahead_checkpoint_id 1237 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1238 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1239 1240 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1241 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1242 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1243 1244 // feedback slow 1245 s3_fast_rep := RegNext(s2_fast_rep) && 1246 !s3_in.feedbacked && 1247 !s3_in.lateKill && 1248 !s3_rep_frm_fetch && 1249 !s3_exception 1250 1251 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1252 1253 // 1254 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1255 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1256 io.feedback_slow.bits.flushState := s3_in.ptwBack 1257 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1258 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1259 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1260 1261 io.vec_stu_io.feedbackSlow.valid := RegNext(s2_vec_feedback.valid && !s2_out.uop.robIdx.needFlush(io.redirect)) 1262 io.vec_stu_io.feedbackSlow.bits := RegNext(s2_vec_feedback.bits) 1263 1264 io.ldu_io.ldCancel.ld2Cancel := s3_valid && s3_ld_flow && ( // is load 1265 io.ldu_io.lsq.ldin.bits.rep_info.need_rep || s3_in.mmio // exe fail or is mmio 1266 ) 1267 1268 // data from dcache hit 1269 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1270 s3_ld_raw_data_frm_cache.respDcacheData := io.ldu_io.dcache.resp.bits.data_delayed 1271 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1272 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1273 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1274 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1275 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, false.B, s2_valid) || s3_fwd_frm_d_chan_valid 1276 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1277 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, false.B, s2_valid) 1278 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1279 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1280 1281 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1282 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1283 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1284 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1285 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1286 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1287 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1288 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1289 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1290 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1291 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1292 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1293 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1294 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1295 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1296 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1297 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1298 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1299 )) 1300 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1301 1302 // FIXME: add 1 cycle delay ? 1303 io.ldout.bits := s3_out.bits 1304 io.ldout.bits.data := s3_ld_data_frm_cache 1305 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow && !s3_isvec 1306 1307 // for uncache 1308 io.ldu_io.lsq.uncache.ready := true.B 1309 1310 // fast load to load forward 1311 if (EnableLoadToLoadForward) { 1312 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1313 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1314 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1315 } else { 1316 io.ldu_io.l2l_fwd_out.valid := false.B 1317 io.ldu_io.l2l_fwd_out.data := DontCare 1318 io.ldu_io.l2l_fwd_out.dly_ld_err := DontCare 1319 } 1320 1321 // hybrid unit writeback to rob 1322 // delay params 1323 val SelectGroupSize = RollbackGroupSize 1324 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1325 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1326 val TotalDelayCycles = TotalSelectCycles - 2 1327 1328 // writeback 1329 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1330 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1331 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1332 1333 sx_can_go := sx_ready.head 1334 for (i <- 0 until TotalDelayCycles + 1) { 1335 if (i == 0) { 1336 sx_valid(i) := s3_valid && 1337 !s3_ld_flow && 1338 !s3_in.feedbacked && 1339 !s3_in.mmio 1340 sx_in(i) := s3_out.bits 1341 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1342 } else { 1343 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1344 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1345 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1346 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1347 1348 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1349 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1350 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1351 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1352 } 1353 } 1354 1355 val sx_last_valid = sx_valid.takeRight(1).head 1356 val sx_last_ready = sx_ready.takeRight(1).head 1357 val sx_last_in = sx_in.takeRight(1).head 1358 1359 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1360 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && FuType.isStore(sx_last_in.uop.fuType) 1361 io.stout.bits := sx_last_in 1362 1363 // trigger 1364 val ld_trigger = FuType.isLoad(io.ldout.bits.uop.fuType) 1365 val last_valid_data = RegEnable(io.ldout.bits.data, io.stout.fire) 1366 val hit_ld_addr_trig_hit_vec = Wire(Vec(TriggerNum, Bool())) 1367 val lq_ld_addr_trig_hit_vec = RegNext(io.ldu_io.lsq.trigger.lqLoadAddrTriggerHitVec) 1368 (0 until TriggerNum).map{i => { 1369 val tdata2 = RegNext(RegNext(io.ldu_io.trigger(i).tdata2)) 1370 val matchType = RegNext(RegNext(io.ldu_io.trigger(i).matchType)) 1371 val tEnable = RegNext(RegNext(io.ldu_io.trigger(i).tEnable)) 1372 1373 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s3_in.vaddr), tdata2, matchType, tEnable) 1374 io.ldu_io.trigger(i).addrHit := Mux(io.ldout.valid && ld_trigger, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1375 }} 1376 io.ldu_io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1377 1378 // FIXME: please move this part to LoadQueueReplay 1379 io.ldu_io.debug_ls := DontCare 1380 io.stu_io.debug_ls := DontCare 1381 io.stu_io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1382 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1383 1384 // Topdown 1385 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1386 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1387 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1388 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1389 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1390 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1391 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.ldu_io.dcache.resp.bits.real_miss 1392 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1393 1394 // perf cnt 1395 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1396 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1397 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1398 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1399 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1400 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1401 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1402 XSPerfAccumulate("s0_stall_ld_dcache", s0_valid && !io.ldu_io.dcache.req.ready) 1403 XSPerfAccumulate("s0_stall_st_dcache", s0_valid && !io.stu_io.dcache.req.ready) 1404 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1405 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1406 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1407 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1408 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1409 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1410 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1411 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1412 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1413 1414 XSPerfAccumulate("s1_in_valid", s1_valid) 1415 XSPerfAccumulate("s1_in_fire", s1_fire) 1416 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1417 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1418 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1419 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1420 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1421 1422 XSPerfAccumulate("s2_in_valid", s2_valid) 1423 XSPerfAccumulate("s2_in_fire", s2_fire) 1424 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1425 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.ldu_io.dcache.resp.bits.miss) 1426 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1427 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1428 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1429 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1430 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1431 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1432 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1433 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1434 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && io.ldu_io.dcache.s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1435 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss) // prefetch req miss in l1 1436 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.ldu_io.dcache.resp.bits.miss) // prefetch req hit in l1 1437 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss && !io.ldu_io.dcache.s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1438 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1439 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1440 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1441 1442 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1443 1444 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1445 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1446 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1447 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1448 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1449 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1450 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1451 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1452 1453 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1454 // hardware performance counter 1455 val perfEvents = Seq( 1456 ("load_s0_in_fire ", s0_fire ), 1457 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1458 ("stall_dcache ", s0_valid && s0_can_go && !io.ldu_io.dcache.req.ready ), 1459 ("load_s1_in_fire ", s0_fire ), 1460 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1461 ("load_s2_in_fire ", s1_fire ), 1462 ("load_s2_dcache_miss ", s2_fire && io.ldu_io.dcache.resp.bits.miss ), 1463 ) 1464 generatePerfEvent() 1465}