xref: /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1package xiangshan.backend.exu
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import xiangshan.backend.fu.{CSRFileIO, FenceIO}
8import xiangshan.backend.Bundles._
9import xiangshan.backend.issue.SchdBlockParams
10import xiangshan.{HasXSParameter, Redirect, XSBundle}
11import utility._
12import xiangshan.backend.fu.FuConfig.{AluCfg, BrhCfg}
13import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm}
14import xiangshan.backend.fu.fpu.Bundles.Frm
15
16class ExuBlock(params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
17  override def shouldBeInlined: Boolean = false
18
19  val exus: Seq[ExeUnit] = params.issueBlockParams.flatMap(_.exuBlockParams.map(x => LazyModule(x.genExuModule)))
20
21  lazy val module = new ExuBlockImp(this)(p, params)
22}
23
24class ExuBlockImp(
25  override val wrapper: ExuBlock
26)(implicit
27  p: Parameters,
28  params: SchdBlockParams
29) extends LazyModuleImp(wrapper) {
30  val io = IO(new ExuBlockIO)
31
32  private val exus = wrapper.exus.map(_.module)
33
34  private val ins: collection.IndexedSeq[DecoupledIO[ExuInput]] = io.in.flatten
35  private val outs: collection.IndexedSeq[DecoupledIO[ExuOutput]] = io.out.flatten
36
37  (ins zip exus zip outs).foreach { case ((input, exu), output) =>
38    exu.io.flush <> io.flush
39    exu.io.csrio.foreach(exuio => io.csrio.get <> exuio)
40    exu.io.fenceio.foreach(exuio => io.fenceio.get <> exuio)
41    exu.io.frm.foreach(exuio => exuio := RegNext(io.frm.get))  // each vf exu pipe frm from csr
42    exu.io.vxrm.foreach(exuio => io.vxrm.get <> exuio)
43    exu.io.vlIsZero.foreach(exuio => io.vlIsZero.get := exuio)
44    exu.io.vlIsVlmax.foreach(exuio => io.vlIsVlmax.get := exuio)
45    exu.io.vtype.foreach(exuio => io.vtype.get := exuio)
46    exu.io.in <> input
47    output <> exu.io.out
48//    if (exu.wrapper.exuParams.fuConfigs.contains(AluCfg) || exu.wrapper.exuParams.fuConfigs.contains(BrhCfg)){
49//      XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
50//    }
51    XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
52  }
53  val aluFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(AluCfg)).map(_.io.in.fire)
54  for (i <- 0 until (aluFireSeq.size + 1)){
55    XSPerfAccumulate(s"alu_fire_${i}_cnt", PopCount(aluFireSeq) === i.U)
56  }
57  val brhFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(BrhCfg)).map(_.io.in.fire)
58  for (i <- 0 until (brhFireSeq.size + 1)) {
59    XSPerfAccumulate(s"brh_fire_${i}_cnt", PopCount(brhFireSeq) === i.U)
60  }
61}
62
63class ExuBlockIO(implicit p: Parameters, params: SchdBlockParams) extends XSBundle {
64  val flush = Flipped(ValidIO(new Redirect))
65  // in(i)(j): issueblock(i), exu(j)
66  val in: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(params.genExuInputBundle)
67  // out(i)(j): issueblock(i), exu(j).
68  val out: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = params.genExuOutputDecoupledBundle
69
70  val csrio = Option.when(params.hasCSR)(new CSRFileIO)
71  val fenceio = Option.when(params.hasFence)(new FenceIO)
72  val frm = Option.when(params.needSrcFrm)(Input(Frm()))
73  val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm()))
74  val vtype = Option.when(params.writeVConfig)((Valid(new VType)))
75  val vlIsZero = Option.when(params.writeVConfig)(Output(Bool()))
76  val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool()))
77}
78