1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b0_0000_0000") 69 def FMVXF = BitPat("b1_1000_0000") //for fmv_x_d & fmv_x_w 70 } 71 72 object VlduType { 73 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 74 // only unit-stride use lumop 75 // mop [1:0] 76 // 0 0 : unit-stride 77 // 0 1 : indexed-unordered 78 // 1 0 : strided 79 // 1 1 : indexed-ordered 80 // lumop[4:0] 81 // 0 0 0 0 0 : unit-stride load 82 // 0 1 0 0 0 : unit-stride, whole register load 83 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 84 // 1 0 0 0 0 : unit-stride fault-only-first 85 def vle = "b00_00_00000".U 86 def vlr = "b00_00_01000".U 87 def vlm = "b00_00_01011".U 88 def vleff = "b00_00_10000".U 89 def vluxe = "b00_01_00000".U 90 def vlse = "b00_10_00000".U 91 def vloxe = "b00_11_00000".U 92 93 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 94 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 95 def isMasked(fuOpType: UInt): Bool = fuOpType === vlm 96 } 97 98 object VstuType { 99 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 100 // only unit-stride use sumop 101 // mop [1:0] 102 // 0 0 : unit-stride 103 // 0 1 : indexed-unordered 104 // 1 0 : strided 105 // 1 1 : indexed-ordered 106 // sumop[4:0] 107 // 0 0 0 0 0 : unit-stride load 108 // 0 1 0 0 0 : unit-stride, whole register load 109 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 110 def vse = "b00_00_00000".U 111 def vsr = "b00_00_01000".U 112 def vsm = "b00_00_01011".U 113 def vsuxe = "b00_01_00000".U 114 def vsse = "b00_10_00000".U 115 def vsoxe = "b00_11_00000".U 116 117 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 118 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 119 } 120 121 object IF2VectorType { 122 // use last 2 bits for vsew 123 def iDup2Vec = "b1_00".U 124 def fDup2Vec = "b1_01".U 125 def immDup2Vec = "b1_10".U 126 def i2Vec = "b0_00".U 127 def f2Vec = "b0_01".U 128 def imm2Vec = "b0_10".U 129 def needDup(bits: UInt): Bool = bits(2) 130 def isImm(bits: UInt): Bool = bits(1) 131 } 132 133 object CommitType { 134 def NORMAL = "b000".U // int/fp 135 def BRANCH = "b001".U // branch 136 def LOAD = "b010".U // load 137 def STORE = "b011".U // store 138 139 def apply() = UInt(3.W) 140 def isFused(commitType: UInt): Bool = commitType(2) 141 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 142 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 143 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 144 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 145 } 146 147 object RedirectLevel { 148 def flushAfter = "b0".U 149 def flush = "b1".U 150 151 def apply() = UInt(1.W) 152 // def isUnconditional(level: UInt) = level(1) 153 def flushItself(level: UInt) = level(0) 154 // def isException(level: UInt) = level(1) && level(0) 155 } 156 157 object ExceptionVec { 158 val ExceptionVecSize = 16 159 def apply() = Vec(ExceptionVecSize, Bool()) 160 } 161 162 object PMAMode { 163 def R = "b1".U << 0 //readable 164 def W = "b1".U << 1 //writeable 165 def X = "b1".U << 2 //executable 166 def I = "b1".U << 3 //cacheable: icache 167 def D = "b1".U << 4 //cacheable: dcache 168 def S = "b1".U << 5 //enable speculative access 169 def A = "b1".U << 6 //enable atomic operation, A imply R & W 170 def C = "b1".U << 7 //if it is cacheable is configable 171 def Reserved = "b0".U 172 173 def apply() = UInt(7.W) 174 175 def read(mode: UInt) = mode(0) 176 def write(mode: UInt) = mode(1) 177 def execute(mode: UInt) = mode(2) 178 def icache(mode: UInt) = mode(3) 179 def dcache(mode: UInt) = mode(4) 180 def speculate(mode: UInt) = mode(5) 181 def atomic(mode: UInt) = mode(6) 182 def configable_cache(mode: UInt) = mode(7) 183 184 def strToMode(s: String) = { 185 var result = 0.U(8.W) 186 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 187 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 188 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 189 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 190 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 191 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 192 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 193 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 194 result 195 } 196 } 197 198 199 object CSROpType { 200 def jmp = "b000".U 201 def wrt = "b001".U 202 def set = "b010".U 203 def clr = "b011".U 204 def wfi = "b100".U 205 def wrti = "b101".U 206 def seti = "b110".U 207 def clri = "b111".U 208 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 209 } 210 211 // jump 212 object JumpOpType { 213 def jal = "b00".U 214 def jalr = "b01".U 215 def auipc = "b10".U 216// def call = "b11_011".U 217// def ret = "b11_100".U 218 def jumpOpisJalr(op: UInt) = op(0) 219 def jumpOpisAuipc(op: UInt) = op(1) 220 } 221 222 object FenceOpType { 223 def fence = "b10000".U 224 def sfence = "b10001".U 225 def fencei = "b10010".U 226 def nofence= "b00000".U 227 } 228 229 object ALUOpType { 230 // shift optype 231 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 232 def sll = "b000_0001".U // sll: src1 << src2 233 234 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 235 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 236 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 237 238 def srl = "b000_0101".U // srl: src1 >> src2 239 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 240 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 241 242 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 243 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 244 245 // RV64 32bit optype 246 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 247 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 248 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 249 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 250 251 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 252 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 253 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 254 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 255 256 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 257 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 258 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 259 def rolw = "b001_1100".U 260 def rorw = "b001_1101".U 261 262 // ADD-op 263 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 264 def add = "b010_0001".U // add: src1 + src2 265 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 266 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 267 268 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 269 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 270 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 271 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 272 273 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 274 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 275 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 276 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 277 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 278 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 279 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 280 281 // SUB-op: src1 - src2 282 def sub = "b011_0000".U 283 def sltu = "b011_0001".U 284 def slt = "b011_0010".U 285 def maxu = "b011_0100".U 286 def minu = "b011_0101".U 287 def max = "b011_0110".U 288 def min = "b011_0111".U 289 290 // branch 291 def beq = "b111_0000".U 292 def bne = "b111_0010".U 293 def blt = "b111_1000".U 294 def bge = "b111_1010".U 295 def bltu = "b111_1100".U 296 def bgeu = "b111_1110".U 297 298 // misc optype 299 def and = "b100_0000".U 300 def andn = "b100_0001".U 301 def or = "b100_0010".U 302 def orn = "b100_0011".U 303 def xor = "b100_0100".U 304 def xnor = "b100_0101".U 305 def orcb = "b100_0110".U 306 307 def sextb = "b100_1000".U 308 def packh = "b100_1001".U 309 def sexth = "b100_1010".U 310 def packw = "b100_1011".U 311 312 def revb = "b101_0000".U 313 def rev8 = "b101_0001".U 314 def pack = "b101_0010".U 315 def orh48 = "b101_0011".U 316 317 def szewl1 = "b101_1000".U 318 def szewl2 = "b101_1001".U 319 def szewl3 = "b101_1010".U 320 def byte2 = "b101_1011".U 321 322 def andlsb = "b110_0000".U 323 def andzexth = "b110_0001".U 324 def orlsb = "b110_0010".U 325 def orzexth = "b110_0011".U 326 def xorlsb = "b110_0100".U 327 def xorzexth = "b110_0101".U 328 def orcblsb = "b110_0110".U 329 def orcbzexth = "b110_0111".U 330 331 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 332 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 333 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 334 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 335 336 def apply() = UInt(FuOpTypeWidth.W) 337 } 338 339 object VSETOpType { 340 val setVlmaxBit = 0 341 val keepVlBit = 1 342 // destTypeBit == 0: write vl to rd 343 // destTypeBit == 1: write vconfig 344 val destTypeBit = 5 345 346 // vsetvli's uop 347 // rs1!=x0, normal 348 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 349 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 350 def uvsetvcfg_xi = "b1010_0000".U 351 def uvsetrd_xi = "b1000_0000".U 352 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 353 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 354 // uop1: w(rd) | vlmax, vtypei -> x[rd] 355 def uvsetvcfg_vlmax_i = "b1010_0001".U 356 def uvsetrd_vlmax_i = "b1000_0001".U 357 // rs1==x0, rd==x0, keep vl, set vtype 358 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 359 def uvsetvcfg_keep_v = "b1010_0010".U 360 361 // vsetvl's uop 362 // rs1!=x0, normal 363 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 364 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 365 def uvsetvcfg_xx = "b0110_0000".U 366 def uvsetrd_xx = "b0100_0000".U 367 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 368 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 369 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 370 def uvsetvcfg_vlmax_x = "b0110_0001".U 371 def uvsetrd_vlmax_x = "b0100_0001".U 372 // rs1==x0, rd==x0, keep vl, set vtype 373 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 374 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 375 def uvmv_v_x = "b0110_0010".U 376 def uvsetvcfg_vv = "b0111_0010".U 377 378 // vsetivli's uop 379 // uop0: w(vconfig) | vli, vtypei -> vconfig 380 // uop1: w(rd) | vli, vtypei -> x[rd] 381 def uvsetvcfg_ii = "b0010_0000".U 382 def uvsetrd_ii = "b0000_0000".U 383 384 def isVsetvl (func: UInt) = func(6) 385 def isVsetvli (func: UInt) = func(7) 386 def isVsetivli(func: UInt) = func(7, 6) === 0.U 387 def isNormal (func: UInt) = func(1, 0) === 0.U 388 def isSetVlmax(func: UInt) = func(setVlmaxBit) 389 def isKeepVl (func: UInt) = func(keepVlBit) 390 // RG: region 391 def writeIntRG(func: UInt) = !func(5) 392 def writeVecRG(func: UInt) = func(5) 393 def readIntRG (func: UInt) = !func(4) 394 def readVecRG (func: UInt) = func(4) 395 // modify fuOpType 396 def keepVl(func: UInt) = func | (1 << keepVlBit).U 397 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 398 } 399 400 object BRUOpType { 401 // branch 402 def beq = "b000_000".U 403 def bne = "b000_001".U 404 def blt = "b000_100".U 405 def bge = "b000_101".U 406 def bltu = "b001_000".U 407 def bgeu = "b001_001".U 408 409 def getBranchType(func: UInt) = func(3, 1) 410 def isBranchInvert(func: UInt) = func(0) 411 } 412 413 object MULOpType { 414 // mul 415 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 416 def mul = "b00000".U 417 def mulh = "b00001".U 418 def mulhsu = "b00010".U 419 def mulhu = "b00011".U 420 def mulw = "b00100".U 421 422 def mulw7 = "b01100".U 423 def isSign(op: UInt) = !op(1) 424 def isW(op: UInt) = op(2) 425 def isH(op: UInt) = op(1, 0) =/= 0.U 426 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 427 } 428 429 object DIVOpType { 430 // div 431 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 432 def div = "b10000".U 433 def divu = "b10010".U 434 def rem = "b10001".U 435 def remu = "b10011".U 436 437 def divw = "b10100".U 438 def divuw = "b10110".U 439 def remw = "b10101".U 440 def remuw = "b10111".U 441 442 def isSign(op: UInt) = !op(1) 443 def isW(op: UInt) = op(2) 444 def isH(op: UInt) = op(0) 445 } 446 447 object MDUOpType { 448 // mul 449 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 450 def mul = "b00000".U 451 def mulh = "b00001".U 452 def mulhsu = "b00010".U 453 def mulhu = "b00011".U 454 def mulw = "b00100".U 455 456 def mulw7 = "b01100".U 457 458 // div 459 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 460 def div = "b10000".U 461 def divu = "b10010".U 462 def rem = "b10001".U 463 def remu = "b10011".U 464 465 def divw = "b10100".U 466 def divuw = "b10110".U 467 def remw = "b10101".U 468 def remuw = "b10111".U 469 470 def isMul(op: UInt) = !op(4) 471 def isDiv(op: UInt) = op(4) 472 473 def isDivSign(op: UInt) = isDiv(op) && !op(1) 474 def isW(op: UInt) = op(2) 475 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 476 def getMulOp(op: UInt) = op(1, 0) 477 } 478 479 object LSUOpType { 480 // load pipeline 481 482 // normal load 483 // Note: bit(1, 0) are size, DO NOT CHANGE 484 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 485 def lb = "b0000".U 486 def lh = "b0001".U 487 def lw = "b0010".U 488 def ld = "b0011".U 489 def lbu = "b0100".U 490 def lhu = "b0101".U 491 def lwu = "b0110".U 492 493 // Zicbop software prefetch 494 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 495 def prefetch_i = "b1000".U // TODO 496 def prefetch_r = "b1001".U 497 def prefetch_w = "b1010".U 498 499 def isPrefetch(op: UInt): Bool = op(3) 500 501 // store pipeline 502 // normal store 503 // bit encoding: | store 00 | size(2bit) | 504 def sb = "b0000".U 505 def sh = "b0001".U 506 def sw = "b0010".U 507 def sd = "b0011".U 508 509 // l1 cache op 510 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 511 def cbo_zero = "b0111".U 512 513 // llc op 514 // bit encoding: | prefetch 11 | suboptype(2bit) | 515 def cbo_clean = "b1100".U 516 def cbo_flush = "b1101".U 517 def cbo_inval = "b1110".U 518 519 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 520 521 // atomics 522 // bit(1, 0) are size 523 // since atomics use a different fu type 524 // so we can safely reuse other load/store's encodings 525 // bit encoding: | optype(4bit) | size (2bit) | 526 def lr_w = "b000010".U 527 def sc_w = "b000110".U 528 def amoswap_w = "b001010".U 529 def amoadd_w = "b001110".U 530 def amoxor_w = "b010010".U 531 def amoand_w = "b010110".U 532 def amoor_w = "b011010".U 533 def amomin_w = "b011110".U 534 def amomax_w = "b100010".U 535 def amominu_w = "b100110".U 536 def amomaxu_w = "b101010".U 537 538 def lr_d = "b000011".U 539 def sc_d = "b000111".U 540 def amoswap_d = "b001011".U 541 def amoadd_d = "b001111".U 542 def amoxor_d = "b010011".U 543 def amoand_d = "b010111".U 544 def amoor_d = "b011011".U 545 def amomin_d = "b011111".U 546 def amomax_d = "b100011".U 547 def amominu_d = "b100111".U 548 def amomaxu_d = "b101011".U 549 550 def size(op: UInt) = op(1,0) 551 } 552 553 object BKUOpType { 554 555 def clmul = "b000000".U 556 def clmulh = "b000001".U 557 def clmulr = "b000010".U 558 def xpermn = "b000100".U 559 def xpermb = "b000101".U 560 561 def clz = "b001000".U 562 def clzw = "b001001".U 563 def ctz = "b001010".U 564 def ctzw = "b001011".U 565 def cpop = "b001100".U 566 def cpopw = "b001101".U 567 568 // 01xxxx is reserve 569 def aes64es = "b100000".U 570 def aes64esm = "b100001".U 571 def aes64ds = "b100010".U 572 def aes64dsm = "b100011".U 573 def aes64im = "b100100".U 574 def aes64ks1i = "b100101".U 575 def aes64ks2 = "b100110".U 576 577 // merge to two instruction sm4ks & sm4ed 578 def sm4ed0 = "b101000".U 579 def sm4ed1 = "b101001".U 580 def sm4ed2 = "b101010".U 581 def sm4ed3 = "b101011".U 582 def sm4ks0 = "b101100".U 583 def sm4ks1 = "b101101".U 584 def sm4ks2 = "b101110".U 585 def sm4ks3 = "b101111".U 586 587 def sha256sum0 = "b110000".U 588 def sha256sum1 = "b110001".U 589 def sha256sig0 = "b110010".U 590 def sha256sig1 = "b110011".U 591 def sha512sum0 = "b110100".U 592 def sha512sum1 = "b110101".U 593 def sha512sig0 = "b110110".U 594 def sha512sig1 = "b110111".U 595 596 def sm3p0 = "b111000".U 597 def sm3p1 = "b111001".U 598 } 599 600 object BTBtype { 601 def B = "b00".U // branch 602 def J = "b01".U // jump 603 def I = "b10".U // indirect 604 def R = "b11".U // return 605 606 def apply() = UInt(2.W) 607 } 608 609 object SelImm { 610 def IMM_X = "b0111".U 611 def IMM_S = "b1110".U 612 def IMM_SB = "b0001".U 613 def IMM_U = "b0010".U 614 def IMM_UJ = "b0011".U 615 def IMM_I = "b0100".U 616 def IMM_Z = "b0101".U 617 def INVALID_INSTR = "b0110".U 618 def IMM_B6 = "b1000".U 619 620 def IMM_OPIVIS = "b1001".U 621 def IMM_OPIVIU = "b1010".U 622 def IMM_VSETVLI = "b1100".U 623 def IMM_VSETIVLI = "b1101".U 624 def IMM_LUI32 = "b1011".U 625 def IMM_VRORVI = "b1111".U 626 627 def X = BitPat("b0000") 628 629 def apply() = UInt(4.W) 630 631 def mkString(immType: UInt) : String = { 632 val strMap = Map( 633 IMM_S.litValue -> "S", 634 IMM_SB.litValue -> "SB", 635 IMM_U.litValue -> "U", 636 IMM_UJ.litValue -> "UJ", 637 IMM_I.litValue -> "I", 638 IMM_Z.litValue -> "Z", 639 IMM_B6.litValue -> "B6", 640 IMM_OPIVIS.litValue -> "VIS", 641 IMM_OPIVIU.litValue -> "VIU", 642 IMM_VSETVLI.litValue -> "VSETVLI", 643 IMM_VSETIVLI.litValue -> "VSETIVLI", 644 IMM_LUI32.litValue -> "LUI32", 645 IMM_VRORVI.litValue -> "VRORVI", 646 INVALID_INSTR.litValue -> "INVALID", 647 ) 648 strMap(immType.litValue) 649 } 650 651 def getImmUnion(immType: UInt) : Imm = { 652 val iuMap = Map( 653 IMM_S.litValue -> ImmUnion.S, 654 IMM_SB.litValue -> ImmUnion.B, 655 IMM_U.litValue -> ImmUnion.U, 656 IMM_UJ.litValue -> ImmUnion.J, 657 IMM_I.litValue -> ImmUnion.I, 658 IMM_Z.litValue -> ImmUnion.Z, 659 IMM_B6.litValue -> ImmUnion.B6, 660 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 661 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 662 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 663 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 664 IMM_LUI32.litValue -> ImmUnion.LUI32, 665 IMM_VRORVI.litValue -> ImmUnion.VRORVI, 666 ) 667 iuMap(immType.litValue) 668 } 669 } 670 671 object UopSplitType { 672 def SCA_SIM = "b000000".U // 673 def VSET = "b010001".U // dirty: vset 674 def VEC_VVV = "b010010".U // VEC_VVV 675 def VEC_VXV = "b010011".U // VEC_VXV 676 def VEC_0XV = "b010100".U // VEC_0XV 677 def VEC_VVW = "b010101".U // VEC_VVW 678 def VEC_WVW = "b010110".U // VEC_WVW 679 def VEC_VXW = "b010111".U // VEC_VXW 680 def VEC_WXW = "b011000".U // VEC_WXW 681 def VEC_WVV = "b011001".U // VEC_WVV 682 def VEC_WXV = "b011010".U // VEC_WXV 683 def VEC_EXT2 = "b011011".U // VF2 0 -> V 684 def VEC_EXT4 = "b011100".U // VF4 0 -> V 685 def VEC_EXT8 = "b011101".U // VF8 0 -> V 686 def VEC_VVM = "b011110".U // VEC_VVM 687 def VEC_VXM = "b011111".U // VEC_VXM 688 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 689 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 690 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 691 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 692 def VEC_VRED = "b100100".U // VEC_VRED 693 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 694 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 695 def VEC_M0X = "b101001".U // VEC_M0X 0MV 696 def VEC_MVV = "b101010".U // VEC_MVV VMV 697 def VEC_M0X_VFIRST = "b101011".U // 698 def VEC_VWW = "b101100".U // 699 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 700 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 701 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 702 def VEC_COMPRESS = "b110000".U // vcompress.vm 703 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 704 def VEC_S_LDST = "b110010".U // vector strided load/store 705 def VEC_I_LDST = "b110011".U // vector indexed load/store 706 def VEC_VFV = "b111000".U // VEC_VFV 707 def VEC_VFW = "b111001".U // VEC_VFW 708 def VEC_WFW = "b111010".U // VEC_WVW 709 def VEC_VFM = "b111011".U // VEC_VFM 710 def VEC_VFRED = "b111100".U // VEC_VFRED 711 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 712 def VEC_M0M = "b000000".U // VEC_M0M 713 def VEC_MMM = "b000000".U // VEC_MMM 714 def VEC_MVNR = "b000100".U // vmvnr 715 def dummy = "b111111".U 716 717 def X = BitPat("b000000") 718 719 def apply() = UInt(6.W) 720 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 721 } 722 723 object ExceptionNO { 724 def instrAddrMisaligned = 0 725 def instrAccessFault = 1 726 def illegalInstr = 2 727 def breakPoint = 3 728 def loadAddrMisaligned = 4 729 def loadAccessFault = 5 730 def storeAddrMisaligned = 6 731 def storeAccessFault = 7 732 def ecallU = 8 733 def ecallS = 9 734 def ecallM = 11 735 def instrPageFault = 12 736 def loadPageFault = 13 737 // def singleStep = 14 738 def storePageFault = 15 739 def priorities = Seq( 740 breakPoint, // TODO: different BP has different priority 741 instrPageFault, 742 instrAccessFault, 743 illegalInstr, 744 instrAddrMisaligned, 745 ecallM, ecallS, ecallU, 746 storeAddrMisaligned, 747 loadAddrMisaligned, 748 storePageFault, 749 loadPageFault, 750 storeAccessFault, 751 loadAccessFault 752 ) 753 def all = priorities.distinct.sorted 754 def frontendSet = Seq( 755 instrAddrMisaligned, 756 instrAccessFault, 757 illegalInstr, 758 instrPageFault 759 ) 760 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 761 val new_vec = Wire(ExceptionVec()) 762 new_vec.foreach(_ := false.B) 763 select.foreach(i => new_vec(i) := vec(i)) 764 new_vec 765 } 766 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 767 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 768 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 769 partialSelect(vec, fuConfig.exceptionOut) 770 } 771 772 object TopDownCounters extends Enumeration { 773 val NoStall = Value("NoStall") // Base 774 // frontend 775 val OverrideBubble = Value("OverrideBubble") 776 val FtqUpdateBubble = Value("FtqUpdateBubble") 777 // val ControlRedirectBubble = Value("ControlRedirectBubble") 778 val TAGEMissBubble = Value("TAGEMissBubble") 779 val SCMissBubble = Value("SCMissBubble") 780 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 781 val RASMissBubble = Value("RASMissBubble") 782 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 783 val OtherRedirectBubble = Value("OtherRedirectBubble") 784 val FtqFullStall = Value("FtqFullStall") 785 786 val ICacheMissBubble = Value("ICacheMissBubble") 787 val ITLBMissBubble = Value("ITLBMissBubble") 788 val BTBMissBubble = Value("BTBMissBubble") 789 val FetchFragBubble = Value("FetchFragBubble") 790 791 // backend 792 // long inst stall at rob head 793 val DivStall = Value("DivStall") // int div, float div/sqrt 794 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 795 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 796 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 797 // freelist full 798 val IntFlStall = Value("IntFlStall") 799 val FpFlStall = Value("FpFlStall") 800 // dispatch queue full 801 val IntDqStall = Value("IntDqStall") 802 val FpDqStall = Value("FpDqStall") 803 val LsDqStall = Value("LsDqStall") 804 805 // memblock 806 val LoadTLBStall = Value("LoadTLBStall") 807 val LoadL1Stall = Value("LoadL1Stall") 808 val LoadL2Stall = Value("LoadL2Stall") 809 val LoadL3Stall = Value("LoadL3Stall") 810 val LoadMemStall = Value("LoadMemStall") 811 val StoreStall = Value("StoreStall") // include store tlb miss 812 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 813 814 // xs replay (different to gem5) 815 val LoadVioReplayStall = Value("LoadVioReplayStall") 816 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 817 818 // bad speculation 819 val ControlRecoveryStall = Value("ControlRecoveryStall") 820 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 821 val OtherRecoveryStall = Value("OtherRecoveryStall") 822 823 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 824 825 val OtherCoreStall = Value("OtherCoreStall") 826 827 val NumStallReasons = Value("NumStallReasons") 828 } 829} 830