xref: /XiangShan/src/main/scala/top/Top.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
28import openLLC.DummyLLC
29import utility._
30import system._
31import device._
32import chisel3.stage.ChiselGeneratorAnnotation
33import org.chipsalliance.cde.config._
34import freechips.rocketchip.diplomacy._
35import freechips.rocketchip.tile._
36import freechips.rocketchip.tilelink._
37import freechips.rocketchip.amba.axi4._
38import freechips.rocketchip.jtag.JTAGIO
39import chisel3.experimental.{annotate, ChiselAnnotation}
40import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
41
42abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
43  with BindingScope
44{
45  // val misc = LazyModule(new SoCMisc())
46  lazy val dts = DTS(bindingTree)
47  lazy val json = JSON(bindingTree)
48}
49
50class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
51{
52  val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
53  val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
54  val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
55
56  ResourceBinding {
57    val width = ResourceInt(2)
58    val model = "freechips,rocketchip-unknown"
59    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
60    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
61    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
62    Resource(ResourceAnchors.root, "width").bind(width)
63    Resource(ResourceAnchors.soc, "width").bind(width)
64    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
65    def bindManagers(xbar: TLNexusNode) = {
66      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
67        manager.resources.foreach(r => r.bind(manager.toResource))
68      }
69    }
70    if (!enableCHI) {
71      bindManagers(misc.l3_xbar.get.asInstanceOf[TLNexusNode])
72      bindManagers(misc.peripheralXbar.get.asInstanceOf[TLNexusNode])
73    }
74  }
75
76  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
77
78  val core_with_l2 = tiles.map(coreParams =>
79    LazyModule(new XSTile()(p.alter((site, here, up) => {
80      case XSCoreParamsKey => coreParams
81      case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = coreParams.HartId)
82    })))
83  )
84
85  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
86    LazyModule(new HuanCun()(new Config((_, _, _) => {
87      case HCCacheParamsKey => l3param.copy(
88        hartIds = tiles.map(_.HartId),
89        FPGAPlatform = debugOpts.FPGAPlatform
90      )
91      case MaxHartIdBits => p(MaxHartIdBits)
92      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
93      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
94    })))
95  )
96
97  val chi_dummyllc_opt = Option.when(enableCHI)(LazyModule(new DummyLLC(numRNs = NumCores)(p)))
98
99  // receive all prefetch req from cores
100  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
101    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
102  }
103
104  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
105    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
106    case None => None
107  }
108
109  for (i <- 0 until NumCores) {
110    core_with_l2(i).clint_int_node := misc.clint.intnode
111    core_with_l2(i).plic_int_node :*= misc.plic.intnode
112    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
113    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
114    if (!enableCHI) {
115      misc.peripheral_ports.get(i) := core_with_l2(i).tl_uncache
116    }
117    core_with_l2(i).memory_port.foreach(port => (misc.core_to_l3_ports.get)(i) :=* port)
118    memblock_pf_recv_nodes(i).map(recv => {
119      println(s"Connecting Core_${i}'s L1 pf source to L3!")
120      recv := core_with_l2(i).core_l3_pf_port.get
121    })
122  }
123
124  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar.get))
125  l3cacheOpt.map(_.intnode.map(int => {
126    misc.plic.intnode := IntBuffer() := int
127  }))
128
129  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
130    l3cacheOpt.get.rst_nodes.get
131  } else {
132    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
133  }
134
135  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
136    case (source, sink) =>  sink := source
137  })
138
139  l3cacheOpt match {
140    case Some(l3) =>
141      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar.get
142      l3.pf_recv_node.map(recv => {
143        println("Connecting L1 prefetcher to L3!")
144        recv := l3_pf_sender_opt.get
145      })
146      l3.tpmeta_recv_node.foreach(recv => {
147        for ((core, i) <- core_with_l2.zipWithIndex) {
148          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
149          recv := core.core_l3_tpmeta_source_port.get
150        }
151      })
152      l3.tpmeta_send_node.foreach(send => {
153        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
154        broadcast.node := send
155        for ((core, i) <- core_with_l2.zipWithIndex) {
156          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
157          core.core_l3_tpmeta_sink_port.get := broadcast.node
158        }
159      })
160    case None =>
161  }
162
163  chi_dummyllc_opt match {
164    case Some(llc) =>
165      misc.soc_xbar.get := llc.axi4node
166    case None =>
167  }
168
169  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
170    soc.XSTopPrefix.foreach { prefix =>
171      val mod = this.toNamed
172      annotate(new ChiselAnnotation {
173        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
174      })
175    }
176
177    FileRegisters.add("dts", dts)
178    FileRegisters.add("graphml", graphML)
179    FileRegisters.add("json", json)
180    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
181
182    val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
183    val peripheral = IO(new VerilogAXI4Record(misc.peripheral.elts.head.params))
184    val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
185
186    socMisc match {
187      case Some(m) =>
188        m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
189        dontTouch(dma.get)
190      case None =>
191    }
192
193    memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
194    peripheral.viewAs[AXI4Bundle] <> misc.peripheral.elements.head._2
195
196    val io = IO(new Bundle {
197      val clock = Input(Bool())
198      val reset = Input(AsyncReset())
199      val sram_config = Input(UInt(16.W))
200      val extIntrs = Input(UInt(NrExtIntr.W))
201      val pll0_lock = Input(Bool())
202      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
203      val systemjtag = new Bundle {
204        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
205        val reset = Input(AsyncReset()) // No reset allowed on top
206        val mfr_id = Input(UInt(11.W))
207        val part_number = Input(UInt(16.W))
208        val version = Input(UInt(4.W))
209      }
210      val debug_reset = Output(Bool())
211      val rtc_clock = Input(Bool())
212      val cacheable_check = new TLPMAIO()
213      val riscv_halt = Output(Vec(NumCores, Bool()))
214      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
215    })
216
217    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
218    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
219
220    // override LazyRawModuleImp's clock and reset
221    childClock := io.clock.asClock
222    childReset := reset_sync
223
224    // output
225    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
226
227    // input
228    dontTouch(io)
229    dontTouch(memory)
230    misc.module.ext_intrs := io.extIntrs
231    misc.module.rtc_clock := io.rtc_clock
232    misc.module.pll0_lock := io.pll0_lock
233    misc.module.cacheable_check <> io.cacheable_check
234
235    io.pll0_ctrl <> misc.module.pll0_ctrl
236
237    for ((core, i) <- core_with_l2.zipWithIndex) {
238      core.module.io.hartId := i.U
239      io.riscv_halt(i) := core.module.io.cpu_halt
240      core.module.io.reset_vector := io.riscv_rst_vec(i)
241      chi_dummyllc_opt.foreach { case llc =>
242        llc.module.io.rn(i) <> core.module.io.chi.get
243        core.module.io.nodeID.get := i.U // TODO
244      }
245    }
246
247    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
248      // tie off core soft reset
249      for(node <- core_rst_nodes){
250        node.out.head._1 := false.B.asAsyncReset
251      }
252    }
253
254    l3cacheOpt match {
255      case Some(l3) =>
256        l3.pf_recv_node match {
257          case Some(recv) =>
258            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
259            for (i <- 0 until NumCores) {
260              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
261                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
262                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
263              }
264            }
265          case None =>
266        }
267        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
268        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
269      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
270    }
271
272    core_with_l2.foreach { case tile =>
273      tile.module.io.nodeID.foreach { case nodeID =>
274        nodeID := DontCare
275        dontTouch(nodeID)
276      }
277    }
278
279    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
280    misc.module.debug_module_io.clock := io.clock
281    misc.module.debug_module_io.reset := reset_sync
282
283    misc.module.debug_module_io.debugIO.reset := misc.module.reset
284    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
285    // TODO: delay 3 cycles?
286    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
287    // jtag connector
288    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
289      x.jtag        <> io.systemjtag.jtag
290      x.reset       := jtag_reset_sync
291      x.mfr_id      := io.systemjtag.mfr_id
292      x.part_number := io.systemjtag.part_number
293      x.version     := io.systemjtag.version
294    }
295
296    withClockAndReset(io.clock.asClock, reset_sync) {
297      // Modules are reset one by one
298      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
299      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
300      ResetGen(resetChain, reset_sync, !debugOpts.ResetGen)
301    }
302
303  }
304
305  lazy val module = new XSTopImp(this)
306}
307
308object TopMain extends App {
309  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
310
311  // tools: init to close dpi-c when in fpga
312  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
313  val enableDifftest = config(DebugOptionsKey).EnableDifftest
314  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
315  val enableConstantin = config(DebugOptionsKey).EnableConstantin
316  Constantin.init(enableConstantin && !envInFPGA)
317  ChiselDB.init(enableChiselDB && !envInFPGA)
318
319  val soc = if (config(SoCParamsKey).UseXSNoCTop)
320    DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
321  else
322    DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
323
324  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
325
326  // generate difftest bundles (w/o DifftestTopIO)
327  if (enableDifftest) {
328    DifftestModule.finish("XiangShan", false)
329  }
330
331  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
332}
333