1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import chisel3.util.experimental.decode.TruthTable 6import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 7 8class CSRPermitModule extends Module { 9 val io = IO(new CSRPermitIO) 10 11 private val (csrAccess, wen, addr, privState) = ( 12 io.in.csrAccess.valid, 13 io.in.csrAccess.bits.wen, 14 io.in.csrAccess.bits.addr, 15 io.in.privState 16 ) 17 18 private val (mret, sret) = ( 19 io.in.mret, 20 io.in.sret, 21 ) 22 23 private val (tsr, vtsr) = ( 24 io.in.status.tsr, 25 io.in.status.vtsr, 26 ) 27 28 private val isRO = addr(11, 10) === "b11".U 29 30 private val accessTable = TruthTable(Seq( 31 // V PRVM ADDR 32 BitPat("b?__00___00") -> BitPat.Y(), // HU/VU access U 33 BitPat("b?__00___??") -> BitPat.N(), // HU/VU access the others 34 BitPat("b1__01___00") -> BitPat.Y(), // VS access U 35 BitPat("b1__01___01") -> BitPat.Y(), // VS access S 36 BitPat("b1__01___??") -> BitPat.N(), // VS access the others 37 BitPat("b0__01___11") -> BitPat.N(), // HS access M 38 BitPat("b0__01___??") -> BitPat.Y(), // HS access the others 39 BitPat("b0__11___??") -> BitPat.Y(), // M access any 40 ), BitPat.N()) 41 42 private val privilegeLegal = chisel3.util.experimental.decode.decoder( 43 privState.V.asUInt ## privState.PRVM.asUInt ## addr(9, 8), 44 accessTable 45 ).asBool 46 47 private val rwLegal = isRO && wen 48 49 private val csrAccessIllegal = csrAccess && (!privilegeLegal || !rwLegal) 50 51 private val mretIllegal = mret && !privState.isModeM 52 53 private val sretIllegal = sret && ( 54 privState.isModeHS && tsr || privState.isModeVS && vtsr || privState.isModeHUorVU 55 ) 56 57 io.out.illegal := csrAccessIllegal || mretIllegal || sretIllegal 58} 59 60class CSRPermitIO extends Bundle { 61 val in = Input(new Bundle { 62 val csrAccess = ValidIO(new Bundle { 63 val wen = Bool() 64 val addr = UInt(12.W) 65 }) 66 val privState = new PrivState 67 val mret = Bool() 68 val sret = Bool() 69 val status = new Bundle { 70 // Trap SRET 71 val tsr = Bool() 72 // Virtual Trap SRET 73 val vtsr = Bool() 74 } 75 }) 76 77 val out = Output(new Bundle { 78 val illegal = Bool() 79 }) 80} 81