fix(CSR): use GEILEN from IMSICParams (#4520)

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to acce

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction
exception, and attempts from VS-mode to access stopei raise a virtual instruction exception.

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feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handl

feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handled according to their priority.

Therefore, we ensured that all illegal instruction exceptions take
precedence over virtual instruction exceptions.

However, with the implementation of certain extensions like Smcsrind and
Smstateen, we encounter scenarios where virtual instruction exceptions
must take precedence over illegal instruction exceptions triggered.

For instance, when mstateen0.csrind is set to 1 and hstateen0.csrind is
0, a virtual instruction exception should be raised if VS mode attempts
to access sireg. However, if the vsiselect value is reserved in this
situation, an illegal instruction exception will be raised instead. If
these checks are treated as being at the same priority level, an illegal
instruction exception would ultimately be raised.

In reality, a virtual instruction exception should take precedence
because when the extension is disabled, we should not even evaluate the
value of vsiselect.

Therefore, we divided the sources of exceptions caused by CSR access
into several categories: M-level, S-level, privilege level,
virtualization level, and indirect access level.

Among them, M-level and S-level will only raise illegal instruction
exceptions, the privilege level will raise both illegal instruction and
virtual instruction exceptions, the virtualization level will raise
virtual instruction exceptions, and indirect access will raise both
illegal instruction and virtual instruction exceptions. Therefore, we
handle the exceptions from the previous levels in the same way, and only
check for exceptions caused by indirect access after ensuring that no
exceptions were raised earlier.

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fix(Smstateen): fix access check when Smstateen extension enable. (#3978)

* fix the access check for custom CSR and remove the illegal instruction
check when accessing S-mode custom CSR from VS mod

fix(Smstateen): fix access check when Smstateen extension enable. (#3978)

* fix the access check for custom CSR and remove the illegal instruction
check when accessing S-mode custom CSR from VS mode. This is because we
can now use the Smstateen extension to control access to custom content
at different privilege levels.

* fix the misjudgment of the U-mode custom CSR.

* fix the missing access check for the stopi CSR in AIA.

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fix(csr): fix read/write stimecmp raise EX_II

* Access stimecmp/vstimecmp raise EX_II when mcounteren.TM = 0 or menvcfg.STCE = 0 in less M mode

fix(aia): fix permit check for aia and fix wen for aia csr. (#3547)

This pr fix aia permit check, and prevents writting sireg/mireg when
read from sireg/mireg.

feat(riscv64): support RISC-V Smrnmi extension (#3480)

sireg: fix the condition of rwSireg_EX_VI. (#3394)

According AIA spec, when vsiselect has the number of an inaccessible
register, attempts from VS-mode to access sireg
(really vsireg) raise a virt

sireg: fix the condition of rwSireg_EX_VI. (#3394)

According AIA spec, when vsiselect has the number of an inaccessible
register, attempts from VS-mode to access sireg
(really vsireg) raise a virtual instruction exception.
But 0x070-0x0ff are external interrupts (IMSIC only), or inaccessible.
And we has implemented IMSIC.

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NewCSR: Move xstatus.vs check to decodeUnit for csrr vl/vlenb

NewCSR: Modify the condition of legal wen

* Wen data legal when !(EX_II | EX_VI)

NewCSR: remove useless code since wfi have been done in decode

NewCSR: add AIA EX check

* Access stopei will raise EX_II in HS mode when mvien.SEIE=1
* Access mireg will raise EX_II when miselect is Illegal value in M mode
* Access sireg will raise EX_II
* 1

NewCSR: add AIA EX check

* Access stopei will raise EX_II in HS mode when mvien.SEIE=1
* Access mireg will raise EX_II when miselect is Illegal value in M mode
* Access sireg will raise EX_II
* 1. when mvien.SEIE=1 && 0x70.U <= siselect <= 0xFF in HS mode
* 2. when siselect is Illegal value in M/HS mode
* 3. when vsiselect > 0x1FF.U in VS mode
* Access sireg will raise EX_VI
* 1. when 0x30.U <= vsiselect <= 0x3F.U or 0x80.U <= vsiselect <= 0xFF.U && vsiselect is odd value in VS mode
* 2. when in VU mode
* Access vsireg will raise EX_II when vsiselect is Illegal value in M/HS mode
* Access sip/sie will raise EX_VI when hvictl.VTI=1 in VS mode

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Support smstateen/ssstateen extension, add stateen0 CSRs

NewCSR: executing dret outside of Debug Mode causes EX_II

NewCSR: fix illegal check

* when write Read-Only CSR will raise EX_II
* Access M mode CSR in VS/VU mode will raise EX_II

NewCSR: fix illegal check when FS/VS is off and fix dirty set of FS/VS

NewCSR: add FS, VS check

* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode
* Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode
* when sstat

NewCSR: add FS, VS check

* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode
* Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode
* when sstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in HS/HU mode
* when sstatus.FS/VS or vsstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in VS/VU mode
* when sstatus.FS/VS or vsstatus.FS/VS is Off, access fp/vec CSR will raise EX_II

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NewCSR: support vu/vs entry debugMode

NewCSR: fix rdata when VS mode access VS CSRs by address of S mode

NewCSR: allow access Hypervisor CSRs in HS mode

NewCSR: add illegal check for wfi in DecodeUnit

NewCSR: set accessibility of `htinst` to RW

NewCSR: connected perfevent to newcsr

NewCSR: permit to access Hypervisor level CSRs in M mode

NewCSR: add EX_II and EX_VI for [v]stimecmp RW and fp/vec insts when FS/VS is off

* Access stimecmp/vstimecmp CSR in Non-M mode will raise EX_II when mcounteren.TM=0 || menvcfg.STCE=0
* Access vstim

NewCSR: add EX_II and EX_VI for [v]stimecmp RW and fp/vec insts when FS/VS is off

* Access stimecmp/vstimecmp CSR in Non-M mode will raise EX_II when mcounteren.TM=0 || menvcfg.STCE=0
* Access vstimecmp CSR in VS mode will raise EX_VI when mcounteren.TM=1 && hcounteren.TM=0
* Access vstimecmp CSR in V Mode will raise EX_VI when menvcfg.STCE=1 && henvcfg.STCE=0
* Access HPM CSR will raise EX_II when mcounteren[x]=0 in Non-M mode
* Access vstimecmp will raise EX_II when mcounteren.TM=0 in HS mode or menvcfg.STCE=0 in Non-M mode
* Access stimecmp will raise EX_II when mcounteren.TM=0 in HS/VS mode or menvcfg.STCE=0 in Non-M mode
* Access stimecmp will raise EX_VI when mcounteren.TM=1 && hcounteren.TM=0 or menvcfg.STCE=1 && henvcfg.STCE=0 in VS mode
* Decode fp inst will raise EX_II when sstatus.FS=Off or vsstatus.FS=Off in VS/VU mode
* Decode vec inst will raise EX_II when sstatus.VS=Off or vsstatus.VS=Off in VS/VU mode

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