xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala (revision 4df1e462ec3f28d28ab0b95556426756b5e05396) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import chisel3.util.experimental.decode.TruthTable
6import xiangshan.backend.fu.NewCSR.CSRBundles.{Counteren, PrivState}
7import freechips.rocketchip.rocket.CSRs
8
9class CSRPermitModule extends Module {
10  val io = IO(new CSRPermitIO)
11
12  private val (ren, wen, addr, privState, debugMode) = (
13    io.in.csrAccess.ren,
14    io.in.csrAccess.wen,
15    io.in.csrAccess.addr,
16    io.in.privState,
17    io.in.debugMode
18  )
19
20  private val csrAccess = WireInit(ren || wen)
21
22  private val (mret, sret, wfi) = (
23    io.in.mret,
24    io.in.sret,
25    io.in.wfi,
26  )
27
28  private val (tsr, vtsr) = (
29    io.in.status.tsr,
30    io.in.status.vtsr,
31  )
32
33  private val (tw, vtw) = (
34    io.in.status.tw,
35    io.in.status.vtw
36  )
37
38  private val (tvm, vtvm) = (
39    io.in.status.tvm,
40    io.in.status.vtvm,
41  )
42
43  private val csrIsCustom = io.in.csrIsCustom
44
45  private val (mcounteren, hcounteren, scounteren) = (
46    io.in.status.mcounteren,
47    io.in.status.hcounteren,
48    io.in.status.scounteren,
49  )
50
51  private val (mcounterenTM, hcounterenTM) = (
52    mcounteren(1),
53    hcounteren(1),
54  )
55
56  private val (menvcfg, henvcfg) = (
57    io.in.status.menvcfg,
58    io.in.status.henvcfg,
59  )
60
61  private val (menvcfgSTCE, henvcfgSTCE) = (
62    menvcfg(63),
63    henvcfg(63),
64  )
65
66  private val csrIsRO = addr(11, 10) === "b11".U
67  private val csrIsUnpriv = addr(9, 8) === "b00".U
68  private val csrIsHPM = addr >= CSRs.cycle.U && addr <= CSRs.hpmcounter31.U
69  private val counterAddr = addr(4, 0) // 32 counters
70
71  private val accessTable = TruthTable(Seq(
72    //       V PRVM ADDR
73    BitPat("b0__00___00") -> BitPat.Y(), // HU access U
74    BitPat("b1__00___00") -> BitPat.Y(), // VU access U
75    BitPat("b0__01___00") -> BitPat.Y(), // HS access U
76    BitPat("b0__01___01") -> BitPat.Y(), // HS access S
77    BitPat("b1__01___00") -> BitPat.Y(), // VS access U
78    BitPat("b1__01___01") -> BitPat.Y(), // VS access S
79    BitPat("b0__11___00") -> BitPat.Y(), // M  access HU
80    BitPat("b0__11___01") -> BitPat.Y(), // M  access HS
81    BitPat("b0__11___10") -> BitPat.Y(), // M  access H
82    BitPat("b0__11___11") -> BitPat.Y(), // M  access M
83  ), BitPat.N())
84
85  private val isDebugReg   = addr(11, 4) === "h7b".U
86  private val isTriggerReg = addr(11, 4) === "h7a".U
87
88  private val regularPrivilegeLegal = chisel3.util.experimental.decode.decoder(
89    privState.V.asUInt ## privState.PRVM.asUInt ## addr(9, 8),
90    accessTable
91  ).asBool
92
93  private val privilegeLegal = MuxCase(
94    regularPrivilegeLegal,
95    Seq(
96      isDebugReg   -> debugMode,
97      isTriggerReg -> (debugMode || privState.isModeM),
98    )
99  )
100
101  private val rwIllegal = csrIsRO && wen
102
103  private val csrAccessIllegal = (!privilegeLegal || rwIllegal)
104
105  private val mretIllegal = !privState.isModeM
106
107  private val sretIllegal = sret && (
108    privState.isModeHS && tsr || privState.isModeVS && vtsr || privState.isModeHUorVU
109  )
110
111  private val wfi_EX_II = wfi && (!privState.isModeM && tw)
112  private val wfi_EX_VI = wfi && (privState.isModeVS && vtw && !tw || privState.isModeVU && !tw)
113
114  private val rwSatp_EX_II = csrAccess && privState.isModeHS &&  tvm && (addr === CSRs.satp.U || addr === CSRs.hgatp.U)
115  private val rwSatp_EX_VI = csrAccess && privState.isModeVS && vtvm && (addr === CSRs.satp.U)
116
117  private val rwCustom_EX_II = csrAccess && privState.isModeVS && csrIsCustom
118
119  private val accessHPM = ren && csrIsHPM
120  private val accessHPM_EX_II = accessHPM && (
121    !privState.isModeM && !mcounteren(counterAddr) ||
122    privState.isModeHU && !scounteren(counterAddr)
123  )
124  private val accessHPM_EX_VI = accessHPM && mcounteren(counterAddr) && (
125    privState.isModeVS && !hcounteren(counterAddr) ||
126    privState.isModeVU && (!hcounteren(counterAddr) || !scounteren(counterAddr))
127  )
128
129  private val rwStimecmp_EX_II = csrAccess && ((privState.isModeHS && !mcounterenTM || !privState.isModeM && !menvcfgSTCE) && addr === CSRs.vstimecmp.U ||
130    ((privState.isModeHS || privState.isModeVS) && !mcounterenTM || !privState.isModeM && !menvcfgSTCE) && addr === CSRs.stimecmp.U)
131  private val rwStimecmp_EX_VI = csrAccess && privState.isModeVS && (mcounterenTM && !hcounterenTM || menvcfgSTCE && !henvcfgSTCE) && addr === CSRs.stimecmp.U
132
133  io.out.illegal := csrAccess && csrAccessIllegal || mret && mretIllegal || sret && sretIllegal
134
135  // Todo: check correct
136  io.out.EX_II := io.out.illegal && !privState.isVirtual || wfi_EX_II || rwSatp_EX_II || accessHPM_EX_II || rwStimecmp_EX_II || rwCustom_EX_II
137  io.out.EX_VI := io.out.illegal &&  privState.isVirtual || wfi_EX_VI || rwSatp_EX_VI || accessHPM_EX_VI || rwStimecmp_EX_VI
138
139  io.out.hasLegalWen := io.in.csrAccess.wen && !csrAccessIllegal
140  io.out.hasLegalMret := mret && !mretIllegal
141  io.out.hasLegalSret := sret && !sretIllegal
142  io.out.hasLegalWfi := wfi && !wfi_EX_II && !wfi_EX_VI
143
144  dontTouch(regularPrivilegeLegal)
145}
146
147class CSRPermitIO extends Bundle {
148  val in = Input(new Bundle {
149    val csrAccess = new Bundle {
150      val ren = Bool()
151      val wen = Bool()
152      val addr = UInt(12.W)
153    }
154    val privState = new PrivState
155    val debugMode = Bool()
156    val mret = Bool()
157    val sret = Bool()
158    val wfi = Bool()
159    val csrIsCustom = Bool()
160    val status = new Bundle {
161      // Trap SRET
162      val tsr = Bool()
163      // Virtual Trap SRET
164      val vtsr = Bool()
165      // Timeout Wait
166      val tw = Bool()
167      // Virtual Timeout Wait
168      val vtw = Bool()
169      // Trap Virtual Memory
170      val tvm = Bool()
171      // Virtual Trap Virtual Memory
172      val vtvm = Bool()
173      // Machine level counter enable, access PMC from the level less than M will trap EX_II
174      val mcounteren = UInt(32.W)
175      // Hypervisor level counter enable.
176      // Accessing PMC from VS/VU level will trap EX_VI, if m[x]=1 && h[x]=0
177      val hcounteren = UInt(32.W)
178      // Supervisor level counter enable.
179      // Accessing PMC from **HU level** will trap EX_II, if s[x]=0
180      // Accessing PMC from **VU level** will trap EX_VI, if m[x]=1 && h[x]=1 && s[x]=0
181      val scounteren = UInt(32.W)
182      // Machine environment configuration register.
183      // Accessing stimecmp or vstimecmp from **Non-M level** will trap EX_II, if menvcfg.STCE=0
184      val menvcfg = UInt(64.W)
185      // Hypervisor environment configuration register.
186      // Accessing vstimecmp from ** V level** will trap EX_VI, if menvcfg.STCE=1 && henvcfg.STCE=0
187      val henvcfg = UInt(64.W)
188    }
189  })
190
191  val out = Output(new Bundle {
192    val hasLegalWen = Bool()
193    val hasLegalMret = Bool()
194    val hasLegalSret = Bool()
195    val hasLegalWfi = Bool()
196    // Todo: split illegal into EX_II and EX_VI
197    val illegal = Bool()
198    val EX_II = Bool()
199    val EX_VI = Bool()
200  })
201}
202