xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala (revision cff94300d0b9d006f19133bb2e14b4f5fa8626b9) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import chisel3.util.experimental.decode.TruthTable
6import freechips.rocketchip.rocket.CSRs
7import xiangshan.backend.fu.NewCSR.CSRBundles.{Counteren, PrivState}
8import xiangshan.backend.fu.NewCSR.CSRDefines._
9
10class CSRPermitModule extends Module {
11  val io = IO(new CSRPermitIO)
12
13  private val (ren, wen, addr, privState, debugMode) = (
14    io.in.csrAccess.ren,
15    io.in.csrAccess.wen,
16    io.in.csrAccess.addr,
17    io.in.privState,
18    io.in.debugMode
19  )
20
21  private val csrAccess = WireInit(ren || wen)
22
23  private val (mret, sret, dret) = (
24    io.in.mret,
25    io.in.sret,
26    io.in.dret,
27  )
28
29  private val (tsr, vtsr) = (
30    io.in.status.tsr,
31    io.in.status.vtsr,
32  )
33
34  private val (tvm, vtvm) = (
35    io.in.status.tvm,
36    io.in.status.vtvm,
37  )
38
39  private val csrIsCustom = io.in.csrIsCustom
40
41  private val (mcounteren, hcounteren, scounteren) = (
42    io.in.status.mcounteren,
43    io.in.status.hcounteren,
44    io.in.status.scounteren,
45  )
46
47  private val (mstateen0, hstateen0, sstateen0) = (
48    io.in.status.mstateen0,
49    io.in.status.hstateen0,
50    io.in.status.sstateen0,
51  )
52
53  private val (mcounterenTM, hcounterenTM) = (
54    mcounteren(1),
55    hcounteren(1),
56  )
57
58  private val (menvcfg, henvcfg) = (
59    io.in.status.menvcfg,
60    io.in.status.henvcfg,
61  )
62
63  private val (menvcfgSTCE, henvcfgSTCE) = (
64    menvcfg(63),
65    henvcfg(63),
66  )
67
68  private val (sFSIsOff, sVSIsOff, sOrVsFSIsOff, sOrVsVSIsOff) = (
69    io.in.status.mstatusFSOff,
70    io.in.status.mstatusVSOff,
71    io.in.status.mstatusFSOff || io.in.status.vsstatusFSOff,
72    io.in.status.mstatusVSOff || io.in.status.vsstatusVSOff,
73  )
74
75  private val (miselectIsIllegal, siselectIsIllegal, vsiselectIsIllegal) = (
76    io.in.aia.miselectIsIllegal,
77    io.in.aia.siselectIsIllegal,
78    io.in.aia.vsiselectIsIllegal,
79  )
80
81  private val (siselect, vsiselect) = (
82    io.in.aia.siselect,
83    io.in.aia.vsiselect,
84  )
85
86  private val (mvienSEIE, hvictlVTI) = (
87    io.in.aia.mvienSEIE,
88    io.in.aia.hvictlVTI,
89  )
90
91  private val csrIsRO = addr(11, 10) === "b11".U
92  private val csrIsUnpriv = addr(9, 8) === "b00".U
93  private val csrIsM = addr(9, 8) === "b11".U
94  private val csrIsHPM = addr >= CSRs.cycle.U && addr <= CSRs.hpmcounter31.U
95  private val csrIsFp = Seq(CSRs.fflags, CSRs.frm, CSRs.fcsr).map(_.U === addr).reduce(_ || _)
96  private val csrIsVec = Seq(CSRs.vstart, CSRs.vxsat, CSRs.vxrm, CSRs.vcsr, CSRs.vtype).map(_.U === addr).reduce(_ || _)
97  private val csrIsWritableVec = Seq(CSRs.vstart, CSRs.vxsat, CSRs.vxrm, CSRs.vcsr).map(_.U === addr).reduce(_ || _)
98  private val counterAddr = addr(4, 0) // 32 counters
99
100  private val accessTable = TruthTable(Seq(
101    //       V PRVM ADDR
102    BitPat("b0__00___00") -> BitPat.Y(), // HU access U
103    BitPat("b1__00___00") -> BitPat.Y(), // VU access U
104    BitPat("b0__01___00") -> BitPat.Y(), // HS access U
105    BitPat("b0__01___01") -> BitPat.Y(), // HS access S
106    BitPat("b0__01___10") -> BitPat.Y(), // HS access H
107    BitPat("b1__01___00") -> BitPat.Y(), // VS access U
108    BitPat("b1__01___01") -> BitPat.Y(), // VS access S
109    BitPat("b0__11___00") -> BitPat.Y(), // M  access HU
110    BitPat("b0__11___01") -> BitPat.Y(), // M  access HS
111    BitPat("b0__11___10") -> BitPat.Y(), // M  access H
112    BitPat("b0__11___11") -> BitPat.Y(), // M  access M
113  ), BitPat.N())
114
115  private val regularPrivilegeLegal = chisel3.util.experimental.decode.decoder(
116    privState.V.asUInt ## privState.PRVM.asUInt ## addr(9, 8),
117    accessTable
118  ).asBool
119
120  private val isDebugReg   = addr(11, 4) === "h7b".U
121  private val privilegeLegal = Mux(isDebugReg, debugMode, regularPrivilegeLegal || debugMode)
122
123  private val rwIllegal = csrIsRO && wen
124
125  private val mret_EX_II = mret && !privState.isModeM
126  private val mret_EX_VI = false.B
127  private val mretIllegal = mret_EX_II || mret_EX_VI
128
129  private val sret_EX_II = sret && (privState.isModeHU || privState.isModeHS && tsr)
130  private val sret_EX_VI = sret && (privState.isModeVU || privState.isModeVS && vtsr)
131  private val sretIllegal = sret_EX_II || sret_EX_VI
132
133  private val dret_EX_II = dret && !debugMode
134  private val dretIllegal = dret_EX_II
135
136  private val rwSatp_EX_II = csrAccess && privState.isModeHS &&  tvm && (addr === CSRs.satp.U || addr === CSRs.hgatp.U)
137  private val rwSatp_EX_VI = csrAccess && privState.isModeVS && vtvm && (addr === CSRs.satp.U)
138
139  private val rwCustom_EX_II = csrAccess && privState.isModeVS && csrIsCustom
140
141  private val accessHPM = ren && csrIsHPM
142  private val accessHPM_EX_II = accessHPM && (
143    !privState.isModeM && !mcounteren(counterAddr) ||
144    privState.isModeHU && !scounteren(counterAddr)
145  )
146  private val accessHPM_EX_VI = accessHPM && mcounteren(counterAddr) && (
147    privState.isModeVS && !hcounteren(counterAddr) ||
148    privState.isModeVU && (!hcounteren(counterAddr) || !scounteren(counterAddr))
149  )
150
151  /**
152   * Sm/Ssstateen0 begin
153   */
154  // SE0 bit 63
155  private val csrIsHstateen0 = (addr === CSRs.hstateen0.U)
156  private val csrIsSstateen0 = (addr === CSRs.sstateen0.U)
157  private val csrIsStateen0 = csrIsHstateen0 || csrIsSstateen0
158  private val accessStateen0_EX_II = csrIsStateen0 && !privState.isModeM && !mstateen0.SE0.asBool
159  private val accessStateen0_EX_VI = csrIsSstateen0 && mstateen0.SE0.asBool && privState.isVirtual && !hstateen0.SE0.asBool ||
160    csrIsHstateen0 && mstateen0.SE0.asBool && privState.isVirtual
161
162  // ENVCFG bit 62
163  private val csrIsHenvcfg = (addr === CSRs.henvcfg.U)
164  private val csrIsSenvcfg = (addr === CSRs.senvcfg.U)
165  private val csrIsEnvcfg = csrIsHenvcfg || csrIsSenvcfg
166  private val accessEnvcfg_EX_II = csrIsEnvcfg && !privState.isModeM && !mstateen0.ENVCFG.asBool
167  private val accessEnvcfg_EX_VI = csrIsSenvcfg && mstateen0.ENVCFG.asBool && privState.isVirtual && !hstateen0.ENVCFG.asBool ||
168    csrIsHenvcfg && mstateen0.ENVCFG.asBool && privState.isVirtual
169
170  // CSRIND bit 60 indirect reg (Sscsrind extensions), this is not implemented
171  // csr addr S: [0x150, 0x157]     VS: [0x250, 0x257]
172  private val csrIsSi = addr.head(9) === CSRs.siselect.U.head(9)
173  private val csrIsVSi = addr.head(9) === CSRs.vsiselect.U.head(9)
174  private val csrIsIND = csrIsSi || csrIsVSi
175  private val accessIND_EX_II = csrIsIND && !privState.isModeM && !mstateen0.CSRIND.asBool
176  private val accessIND_EX_VI = csrIsSi && mstateen0.CSRIND.asBool && privState.isVirtual && !hstateen0.CSRIND.asBool ||
177    csrIsVSi && mstateen0.CSRIND.asBool && privState.isVirtual
178
179  // AIA bit 59
180  private val ssAiaHaddr = Seq(CSRs.hvien.U, CSRs.hvictl.U, CSRs.hviprio1.U, CSRs.hviprio2.U)
181  private val ssAiaVSaddr = addr === CSRs.vstopi.U
182  private val csrIsAIA = ssAiaHaddr.map(_ === addr).reduce(_ || _) || ssAiaVSaddr
183  private val accessAIA_EX_II = csrIsAIA && !privState.isModeM && !mstateen0.AIA.asBool
184  private val accessAIA_EX_VI = csrIsAIA && mstateen0.AIA.asBool && privState.isVirtual
185
186  // IMSIC bit 58 (Ssaia extension)
187  private val csrIsStopei = addr === CSRs.stopei.U
188  private val csrIsVStopei = addr === CSRs.vstopei.U
189  private val csrIsTpoie = csrIsStopei || csrIsVStopei
190  private val accessTopie_EX_II = csrIsTpoie && !privState.isModeM && !mstateen0.IMSIC.asBool
191  private val accessTopie_EX_VI = csrIsStopei && mstateen0.IMSIC.asBool && privState.isVirtual && !hstateen0.IMSIC.asBool ||
192    csrIsVStopei && mstateen0.IMSIC.asBool && privState.isVirtual
193
194  // CONTEXT bit 57 context reg (Sdtrig extensions), this is not implemented
195  private val csrIsHcontext = (addr === CSRs.hcontext.U)
196  private val csrIsScontext = (addr === CSRs.scontext.U)
197  private val csrIsContext = csrIsHcontext || csrIsScontext
198  private val accessContext_EX_II = csrIsContext && !privState.isModeM && !mstateen0.CONTEXT.asBool
199  private val accessContext_EX_VI = csrIsScontext && mstateen0.CONTEXT.asBool && privState.isVirtual && !hstateen0.CONTEXT.asBool ||
200    csrIsHcontext && mstateen0.CONTEXT.asBool && privState.isVirtual
201
202  // P1P13 bit 56, Read-only 0
203
204  // Custom bit 0
205  // csr addr HVS: [0x6c0, 0x6ff], [0xac0, 0xaff], [0xec0, 0xeff]
206  private val csrIsHVSCustom = (addr(11, 10) =/= "b00".U) && (addr(9, 8) === "b10".U) && (addr(7, 6) === "b11".U)
207  // [0x5c0, 0x5ff], [0x9c0, 0x9ff], [0xdc0, 0xdff]
208  private val csrIsSCustom   = (addr(11, 10) =/= "b00".U) && (addr(9, 8) === "b01".U) && (addr(7, 6) === "b11".U)
209  // [0x800, 0x8ff], [0xcc0, 0xcff]
210  private val csrIsUCustom   = (addr(11, 8) =/= "b1000".U) || (addr(11, 6) =/= "b100011".U)
211  private val allCustom      = csrIsHVSCustom || csrIsSCustom || csrIsUCustom
212  private val accessCustom_EX_II = allCustom && (
213    !privState.isModeM && !mstateen0.C.asBool ||
214      privState.isModeHU && !sstateen0.C.asBool
215  )
216  private val accessCustom_EX_VI = mstateen0.C.asBool && (
217    (csrIsSCustom || csrIsUCustom) && privState.isVirtual && !hstateen0.C.asBool ||
218      csrIsUCustom && privState.isModeVU && hstateen0.C.asBool && !sstateen0.C.asBool
219  )
220
221  val xstateControlAccess_EX_II = csrAccess && (accessStateen0_EX_II || accessEnvcfg_EX_II || accessIND_EX_II || accessAIA_EX_II ||
222    accessTopie_EX_II || accessContext_EX_II || accessCustom_EX_II)
223  val xstateControlAccess_EX_VI = csrAccess && (accessStateen0_EX_VI || accessEnvcfg_EX_VI || accessIND_EX_VI || accessAIA_EX_VI ||
224    accessTopie_EX_VI || accessContext_EX_VI || accessCustom_EX_VI)
225  /**
226   * Sm/Ssstateen end
227   */
228
229  private val rwStimecmp_EX_II = csrAccess && ((privState.isModeHS && !mcounterenTM || !privState.isModeM && !menvcfgSTCE) && addr === CSRs.vstimecmp.U ||
230    ((privState.isModeHS || privState.isModeVS) && !mcounterenTM || !privState.isModeM && !menvcfgSTCE) && addr === CSRs.stimecmp.U)
231  private val rwStimecmp_EX_VI = (csrAccess && privState.isModeVS && (mcounterenTM && !hcounterenTM || menvcfgSTCE && !henvcfgSTCE) ||
232    wen && privState.isModeVS && hvictlVTI) && addr === CSRs.stimecmp.U
233
234  private val fsEffectiveOff = sFSIsOff && !privState.isVirtual || sOrVsFSIsOff && privState.isVirtual
235  private val vsEffectiveOff = sVSIsOff && !privState.isVirtual || sOrVsVSIsOff && privState.isVirtual
236
237  private val fpOff_EX_II  = csrAccess && csrIsFp  && fsEffectiveOff
238  private val vecOff_EX_II = csrAccess && csrIsVec && vsEffectiveOff
239
240  private val fpVec_EX_II = fpOff_EX_II || vecOff_EX_II
241
242  /**
243   * AIA begin
244   */
245  private val rwStopei_EX_II = csrAccess && privState.isModeHS && mvienSEIE && addr === CSRs.stopei.U
246
247  private val rwMireg_EX_II = csrAccess && privState.isModeM && miselectIsIllegal && addr === CSRs.mireg.U
248
249  private val rwSireg_EX_II = csrAccess && ((privState.isModeHS && mvienSEIE && siselect >= 0x70.U && siselect <= 0xFF.U) ||
250    ((privState.isModeM || privState.isModeHS) && siselectIsIllegal) ||
251    (privState.isModeVS && vsiselect > 0x1FF.U)) && addr === CSRs.sireg.U
252  private val rwSireg_EX_VI = csrAccess && (privState.isModeVS && (vsiselect >= 0x30.U && vsiselect <= 0x3F.U) ||
253    privState.isModeVU) && addr === CSRs.sireg.U
254
255  private val rwVSireg_EX_II = csrAccess && (privState.isModeM || privState.isModeHS) && vsiselectIsIllegal && addr === CSRs.vsireg.U
256
257  private val rwSip_Sie_EX_VI = csrAccess && privState.isModeVS && hvictlVTI && (addr === CSRs.sip.U || addr === CSRs.sie.U)
258
259  /**
260   * AIA end
261   */
262
263  // Todo: check correct
264  io.out.EX_II :=  csrAccess && !privilegeLegal && (!privState.isVirtual || privState.isVirtual && csrIsM) ||
265    rwIllegal || mret_EX_II || sret_EX_II || rwSatp_EX_II || accessHPM_EX_II ||
266    rwStimecmp_EX_II || rwCustom_EX_II || fpVec_EX_II || dret_EX_II || xstateControlAccess_EX_II || rwStopei_EX_II ||
267    rwMireg_EX_II || rwSireg_EX_II || rwVSireg_EX_II
268  io.out.EX_VI := (csrAccess && !privilegeLegal && privState.isVirtual && !csrIsM ||
269    mret_EX_VI || sret_EX_VI || rwSatp_EX_VI || accessHPM_EX_VI || rwStimecmp_EX_VI || rwSireg_EX_VI || rwSip_Sie_EX_VI) && !rwIllegal || xstateControlAccess_EX_VI
270
271  io.out.hasLegalWen  := wen  && !(io.out.EX_II || io.out.EX_VI)
272  io.out.hasLegalMret := mret && !mretIllegal
273  io.out.hasLegalSret := sret && !sretIllegal
274  io.out.hasLegalDret := dret && !dretIllegal
275
276  io.out.hasLegalWriteFcsr := wen && csrIsFp && !fsEffectiveOff
277  io.out.hasLegalWriteVcsr := wen && csrIsWritableVec && !vsEffectiveOff
278
279  dontTouch(regularPrivilegeLegal)
280}
281
282class CSRPermitIO extends Bundle {
283  val in = Input(new Bundle {
284    val csrAccess = new Bundle {
285      val ren = Bool()
286      val wen = Bool()
287      val addr = UInt(12.W)
288    }
289    val privState = new PrivState
290    val debugMode = Bool()
291    val mret = Bool()
292    val sret = Bool()
293    val dret = Bool()
294    val csrIsCustom = Bool()
295    val status = new Bundle {
296      // Trap SRET
297      val tsr = Bool()
298      // Virtual Trap SRET
299      val vtsr = Bool()
300      // Trap Virtual Memory
301      val tvm = Bool()
302      // Virtual Trap Virtual Memory
303      val vtvm = Bool()
304      // Machine level counter enable, access PMC from the level less than M will trap EX_II
305      val mcounteren = UInt(32.W)
306      // Hypervisor level counter enable.
307      // Accessing PMC from VS/VU level will trap EX_VI, if m[x]=1 && h[x]=0
308      val hcounteren = UInt(32.W)
309      // Supervisor level counter enable.
310      // Accessing PMC from **HU level** will trap EX_II, if s[x]=0
311      // Accessing PMC from **VU level** will trap EX_VI, if m[x]=1 && h[x]=1 && s[x]=0
312      val scounteren = UInt(32.W)
313      // Machine environment configuration register.
314      // Accessing stimecmp or vstimecmp from **Non-M level** will trap EX_II, if menvcfg.STCE=0
315      val menvcfg = UInt(64.W)
316      // Hypervisor environment configuration register.
317      // Accessing vstimecmp from ** V level** will trap EX_VI, if menvcfg.STCE=1 && henvcfg.STCE=0
318      val henvcfg = UInt(64.W)
319
320      val mstatusFSOff = Bool()
321      val vsstatusFSOff = Bool()
322      val mstatusVSOff = Bool()
323      val vsstatusVSOff = Bool()
324      // Sm/Ssstateen: to control state access
325      val mstateen0 = new MstateenBundle0
326      val hstateen0 = new HstateenBundle0
327      val sstateen0 = new SstateenBundle0
328    }
329    val aia = new Bundle {
330      val miselectIsIllegal = Bool()
331      val siselectIsIllegal = Bool()
332      val vsiselectIsIllegal = Bool()
333      val siselect = UInt(64.W)
334      val vsiselect = UInt(64.W)
335      val mvienSEIE = Bool()
336      val hvictlVTI = Bool()
337    }
338  })
339
340  val out = Output(new Bundle {
341    val hasLegalWen  = Bool()
342    val hasLegalMret = Bool()
343    val hasLegalSret = Bool()
344    val hasLegalDret = Bool()
345    val hasLegalWriteFcsr = Bool()
346    val hasLegalWriteVcsr = Bool()
347    val EX_II = Bool()
348    val EX_VI = Bool()
349  })
350}
351