1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 28import xiangshan.cache.mmu.{TlbRequestIO, TlbHintIO} 29import xiangshan.mem._ 30import xiangshan.backend._ 31import xiangshan.backend.rob.RobLsqIO 32 33class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 34 val isStore = Input(Bool()) 35 val vaddr = Output(UInt(VAddrBits.W)) 36 val vstart = Output(UInt((log2Up(VLEN) + 1).W)) 37 val vl = Output(UInt((log2Up(VLEN) + 1).W)) 38 val gpaddr = Output(UInt(GPAddrBits.W)) 39} 40 41class FwdEntry extends Bundle { 42 val validFast = Bool() // validFast is generated the same cycle with query 43 val valid = Bool() // valid is generated 1 cycle after query request 44 val data = UInt(8.W) // data is generated 1 cycle after query request 45} 46 47// inflight miss block reqs 48class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 49 val block_addr = UInt(PAddrBits.W) 50 val valid = Bool() 51} 52 53class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 54 val canAccept = Output(Bool()) 55 val needAlloc = Vec(LSQEnqWidth, Input(UInt(2.W))) 56 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 57 val resp = Vec(LSQEnqWidth, Output(new LSIdx)) 58} 59 60// Load / Store Queue Wrapper for XiangShan Out of Order LSU 61class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 62 val io = IO(new Bundle() { 63 val hartId = Input(UInt(hartIdLen.W)) 64 val brqRedirect = Flipped(ValidIO(new Redirect)) 65 val stvecFeedback = Vec(VecStorePipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 66 val ldvecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 67 val enq = new LsqEnqIO 68 val ldu = new Bundle() { 69 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 70 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 71 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 72 } 73 val sta = new Bundle() { 74 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 75 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 76 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 77 } 78 val std = new Bundle() { 79 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 80 } 81 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 82 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 83 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 84 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 85 val sbufferVecDifftestInfo = Vec(EnsbufferWidth, Decoupled(new DynInst)) // The vector store difftest needs is 86 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 87 val rob = Flipped(new RobLsqIO) 88 val nuke_rollback = Vec(StorePipelineWidth, Output(Valid(new Redirect))) 89 val nack_rollback = Output(Valid(new Redirect)) 90 val release = Flipped(Valid(new Release)) 91 // val refill = Flipped(Valid(new Refill)) 92 val tl_d_channel = Input(new DcacheToLduForwardIO) 93 val uncacheOutstanding = Input(Bool()) 94 val uncache = new UncacheWordIO 95 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 96 // TODO: implement vector store 97 val vecmmioStout = DecoupledIO(new MemExuOutput(isVector = true)) // vec writeback uncached store 98 val sqEmpty = Output(Bool()) 99 val lq_rep_full = Output(Bool()) 100 val sqFull = Output(Bool()) 101 val lqFull = Output(Bool()) 102 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 103 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 104 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 105 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 106 val lqCanAccept = Output(Bool()) 107 val sqCanAccept = Output(Bool()) 108 val lqDeqPtr = Output(new LqPtr) 109 val sqDeqPtr = Output(new SqPtr) 110 val exceptionAddr = new ExceptionAddrIO 111 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 112 val issuePtrExt = Output(new SqPtr) 113 val l2_hint = Input(Valid(new L2ToL1Hint())) 114 val tlb_hint = Flipped(new TlbHintIO) 115 val force_write = Output(Bool()) 116 val lqEmpty = Output(Bool()) 117 118 // top-down 119 val debugTopDown = new LoadQueueTopDownIO 120 }) 121 122 val loadQueue = Module(new LoadQueue) 123 val storeQueue = Module(new StoreQueue) 124 125 storeQueue.io.hartId := io.hartId 126 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 127 128 129 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 130 // Todo: imm 131 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 132 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 133 134 // io.enq logic 135 // LSQ: send out canAccept when both load queue and store queue are ready 136 // Dispatch: send instructions to LSQ only when they are ready 137 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 138 io.lqCanAccept := loadQueue.io.enq.canAccept 139 io.sqCanAccept := storeQueue.io.enq.canAccept 140 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 141 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 142 io.lqDeqPtr := loadQueue.io.lqDeqPtr 143 io.sqDeqPtr := storeQueue.io.sqDeqPtr 144 for (i <- io.enq.req.indices) { 145 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 146 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 147 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 148 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 149 150 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 151 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 152 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 153 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 154 155 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 156 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 157 } 158 159 // store queue wiring 160 storeQueue.io.brqRedirect <> io.brqRedirect 161 storeQueue.io.vecFeedback <> io.stvecFeedback 162 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 163 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 164 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 165 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 166 storeQueue.io.sbuffer <> io.sbuffer 167 storeQueue.io.sbufferVecDifftestInfo <> io.sbufferVecDifftestInfo 168 storeQueue.io.mmioStout <> io.mmioStout 169 storeQueue.io.vecmmioStout <> io.vecmmioStout 170 storeQueue.io.rob <> io.rob 171 storeQueue.io.exceptionAddr.isStore := DontCare 172 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 173 storeQueue.io.sqDeq <> io.sqDeq 174 storeQueue.io.sqEmpty <> io.sqEmpty 175 storeQueue.io.sqFull <> io.sqFull 176 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 177 storeQueue.io.force_write <> io.force_write 178 179 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 180 181 // load queue wiring 182 loadQueue.io.redirect <> io.brqRedirect 183 loadQueue.io.vecFeedback <> io.ldvecFeedback 184 loadQueue.io.ldu <> io.ldu 185 loadQueue.io.ldout <> io.ldout 186 loadQueue.io.ld_raw_data <> io.ld_raw_data 187 loadQueue.io.rob <> io.rob 188 loadQueue.io.nuke_rollback <> io.nuke_rollback 189 loadQueue.io.nack_rollback <> io.nack_rollback 190 loadQueue.io.replay <> io.replay 191 // loadQueue.io.refill <> io.refill 192 loadQueue.io.tl_d_channel <> io.tl_d_channel 193 loadQueue.io.release <> io.release 194 loadQueue.io.trigger <> io.trigger 195 loadQueue.io.exceptionAddr.isStore := DontCare 196 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 197 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 198 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 199 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 200 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 201 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 202 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 203 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 204 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 205 loadQueue.io.lqFull <> io.lqFull 206 loadQueue.io.lq_rep_full <> io.lq_rep_full 207 loadQueue.io.lqDeq <> io.lqDeq 208 loadQueue.io.l2_hint <> io.l2_hint 209 loadQueue.io.tlb_hint <> io.tlb_hint 210 loadQueue.io.lqEmpty <> io.lqEmpty 211 212 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 213 // s0: commit 214 // s1: exception find 215 // s2: exception triggered 216 // s3: ptr updated & new address 217 // address will be used at the next cycle after exception is triggered 218 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 219 io.exceptionAddr.vstart := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vstart, loadQueue.io.exceptionAddr.vstart) 220 io.exceptionAddr.vl := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vl, loadQueue.io.exceptionAddr.vl) 221 io.exceptionAddr.gpaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.gpaddr, loadQueue.io.exceptionAddr.gpaddr) 222 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 223 224 // naive uncache arbiter 225 val s_idle :: s_load :: s_store :: Nil = Enum(3) 226 val pendingstate = RegInit(s_idle) 227 228 switch(pendingstate){ 229 is(s_idle){ 230 when(io.uncache.req.fire){ 231 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 232 Mux(io.uncacheOutstanding, s_idle, s_store)) 233 } 234 } 235 is(s_load){ 236 when(io.uncache.resp.fire){ 237 pendingstate := s_idle 238 } 239 } 240 is(s_store){ 241 when(io.uncache.resp.fire){ 242 pendingstate := s_idle 243 } 244 } 245 } 246 247 loadQueue.io.uncache := DontCare 248 storeQueue.io.uncache := DontCare 249 loadQueue.io.uncache.req.ready := false.B 250 storeQueue.io.uncache.req.ready := false.B 251 loadQueue.io.uncache.resp.valid := false.B 252 storeQueue.io.uncache.resp.valid := false.B 253 when(loadQueue.io.uncache.req.valid){ 254 io.uncache.req <> loadQueue.io.uncache.req 255 }.otherwise{ 256 io.uncache.req <> storeQueue.io.uncache.req 257 } 258 when (io.uncacheOutstanding) { 259 io.uncache.resp <> loadQueue.io.uncache.resp 260 } .otherwise { 261 when(pendingstate === s_load){ 262 io.uncache.resp <> loadQueue.io.uncache.resp 263 }.otherwise{ 264 io.uncache.resp <> storeQueue.io.uncache.resp 265 } 266 } 267 268 loadQueue.io.debugTopDown <> io.debugTopDown 269 270 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 271 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 272 when (!io.uncacheOutstanding) { 273 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 274 } 275 276 277 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 278 generatePerfEvent() 279} 280 281class LsqEnqCtrl(implicit p: Parameters) extends XSModule 282 with HasVLSUParameters { 283 val io = IO(new Bundle { 284 val redirect = Flipped(ValidIO(new Redirect)) 285 // to dispatch 286 val enq = new LsqEnqIO 287 // from `memBlock.io.lqDeq 288 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 289 // from `memBlock.io.sqDeq` 290 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 291 // from/tp lsq 292 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 293 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 294 val lqFreeCount = Output(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 295 val sqFreeCount = Output(UInt(log2Up(StoreQueueSize + 1).W)) 296 val enqLsq = Flipped(new LsqEnqIO) 297 }) 298 299 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 300 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 301 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 302 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 303 val canAccept = RegInit(false.B) 304 305 val loadEnqVec = io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0)) 306 val storeEnqVec = io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1)) 307 val isLastUopVec = io.enq.req.map(_.bits.lastUop) 308 val vLoadFlow = io.enq.req.map(_.bits.numLsElem) 309 val vStoreFlow = io.enq.req.map(_.bits.numLsElem) 310 val validVLoadFlow = vLoadFlow.zipWithIndex.map{case (vLoadFlowNumItem, index) => Mux(loadEnqVec(index), vLoadFlowNumItem, 0.U)} 311 val validVStoreFlow = vStoreFlow.zipWithIndex.map{case (vStoreFlowNumItem, index) => Mux(storeEnqVec(index), vStoreFlowNumItem, 0.U)} 312 val enqVLoadOffsetNumber = validVLoadFlow.reduce(_ + _) 313 val enqVStoreOffsetNumber = validVStoreFlow.reduce(_ + _) 314 val validVLoadOffset = 0.U +: vLoadFlow.zip(io.enq.needAlloc) 315 .map{case (flow, needAllocItem) => Mux(needAllocItem(0).asBool, flow, 0.U)} 316 .slice(0, validVLoadFlow.length - 1) 317 val validVStoreOffset = 0.U +: vStoreFlow.zip(io.enq.needAlloc) 318 .map{case (flow, needAllocItem) => Mux(needAllocItem(1).asBool, flow, 0.U)} 319 .slice(0, validVStoreFlow.length - 1) 320 val lqAllocNumber = enqVLoadOffsetNumber 321 val sqAllocNumber = enqVStoreOffsetNumber 322 323 io.lqFreeCount := lqCounter 324 io.sqFreeCount := sqCounter 325 // How to update ptr and counter: 326 // (1) by default, updated according to enq/commit 327 // (2) when redirect and dispatch queue is empty, update according to lsq 328 val t1_redirect = RegNext(io.redirect.valid) 329 val t2_redirect = RegNext(t1_redirect) 330 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 331 val t3_update = RegNext(t2_update) 332 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 333 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 334 when (t3_update) { 335 lqPtr := lqPtr - t3_lqCancelCnt 336 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 337 sqPtr := sqPtr - t3_sqCancelCnt 338 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 339 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 340 lqPtr := lqPtr + lqAllocNumber 341 lqCounter := lqCounter + io.lcommit - lqAllocNumber 342 sqPtr := sqPtr + sqAllocNumber 343 sqCounter := sqCounter + io.scommit - sqAllocNumber 344 }.otherwise { 345 lqCounter := lqCounter + io.lcommit 346 sqCounter := sqCounter + io.scommit 347 } 348 349 350 //TODO MaxAllocate and width of lqOffset/sqOffset needs to be discussed 351 val lqMaxAllocate = LSQLdEnqWidth 352 val sqMaxAllocate = LSQStEnqWidth 353 val maxAllocate = lqMaxAllocate max sqMaxAllocate 354 val ldCanAccept = lqCounter >= lqAllocNumber +& lqMaxAllocate.U 355 val sqCanAccept = sqCounter >= sqAllocNumber +& sqMaxAllocate.U 356 // It is possible that t3_update and enq are true at the same clock cycle. 357 // For example, if redirect.valid lasts more than one clock cycle, 358 // after the last redirect, new instructions may enter but previously redirect has not been resolved (updated according to the cancel count from LSQ). 359 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 360 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 361 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(lqPtr.value.getWidth.W))) 362 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(sqPtr.value.getWidth.W))) 363 for ((resp, i) <- io.enq.resp.zipWithIndex) { 364 lqOffset(i) := validVLoadOffset.take(i + 1).reduce(_ + _) 365 resp.lqIdx := lqPtr + lqOffset(i) 366 sqOffset(i) := validVStoreOffset.take(i + 1).reduce(_ + _) 367 resp.sqIdx := sqPtr + sqOffset(i) 368 } 369 370 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 371 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 372 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 373 toLsq.valid := RegNext(do_enq) 374 toLsq.bits := RegEnable(enq.bits, do_enq) 375 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 376 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 377 } 378 379}