1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13 14class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 15{ 16 val csrIn = io.csrio.get 17 val csrOut = io.csrio.get 18 19 val setFsDirty = csrIn.fpu.dirty_fs 20 val setFflags = csrIn.fpu.fflags 21 val setVsDirty = csrIn.vpu.dirty_vs 22 val setVxsat = csrIn.vpu.vxsat 23 val setVstart = csrIn.vpu.set_vstart 24 val setVl = csrIn.vpu.set_vl 25 val setVtype = csrIn.vpu.set_vtype 26 27 val flushPipe = Wire(Bool()) 28 val flush = io.flush.valid 29 30 val (valid, src1, src2, func) = ( 31 io.in.valid, 32 io.in.bits.data.src(0), 33 io.in.bits.data.imm, 34 io.in.bits.ctrl.fuOpType 35 ) 36 37 // split imm from IMM_Z 38 val addr = src2(11, 0) 39 val csri = src2(16, 12) 40 41 import CSRConst._ 42 43 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 44 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 45 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 46 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 47 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 48 private val isWfi = CSROpType.isWfi(func) 49 private val isCSRAcc = CSROpType.isCsrAccess(func) 50 51 val csrMod = Module(new NewCSR) 52 53 private val privState = csrMod.io.out.privState 54 // The real reg value in CSR, with no read mask 55 private val regOut = csrMod.io.out.regOut 56 // The read data with read mask 57 private val rdata = csrMod.io.out.rData 58 private val wdata = LookupTree(func, Seq( 59 CSROpType.wrt -> src1, 60 CSROpType.set -> (regOut | src1), 61 CSROpType.clr -> (regOut & (~src1).asUInt), 62 CSROpType.wrti -> csri, 63 CSROpType.seti -> (regOut | csri), 64 CSROpType.clri -> (regOut & (~csri).asUInt), 65 )) 66 67 private val csrAccess = valid && CSROpType.isCsrAccess(func) 68 private val csrWen = valid && CSROpType.notReadOnly(func) 69 70 csrMod.io.in match { 71 case in => 72 in.wen := csrWen 73 in.ren := csrAccess 74 in.addr := addr 75 in.wdata := wdata 76 } 77 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 78 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 79 80 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 81 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 82 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 83 // Todo: shrink the width of trap vector. 84 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 85 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 86 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 87 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 88 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 89 90 csrMod.io.fromRob.commit.fflags := setFflags 91 csrMod.io.fromRob.commit.fsDirty := setFsDirty 92 csrMod.io.fromRob.commit.vxsat.valid := setVxsat 93 csrMod.io.fromRob.commit.vxsat.bits := setVxsat 94 csrMod.io.fromRob.commit.vsDirty := setVsDirty 95 csrMod.io.fromRob.commit.vstart := setVstart 96 csrMod.io.fromRob.commit.vl := setVl 97 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid // Todo: correct vtype 98 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(63) 99 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 100 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 101 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 102 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 103 csrMod.io.fromRob.commit.instNum.valid := false.B // Todo: 104 csrMod.io.fromRob.commit.instNum.bits := 0.U // Todo: 105 106 csrMod.io.mret := isMret 107 csrMod.io.sret := isSret 108 csrMod.io.dret := isDret 109 csrMod.io.wfi := isWfi 110 111 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 112 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 113 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 114 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 115 csrMod.platformIRP.VSEIP := false.B // Todo 116 csrMod.platformIRP.VSTIP := false.B // Todo 117 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 118 119 private val imsic = Module(new IMSIC) 120 imsic.i.hartId := io.csrin.get.hartId 121 imsic.i.setIpNumValidVec2 := io.csrin.get.setIpNumValidVec2 122 imsic.i.setIpNum.valid := true.B // Todo: 123 imsic.i.setIpNum.bits := io.csrin.get.setIpNum // Todo: 124 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 125 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 126 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 127 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 128 imsic.i.csr.vgein := csrMod.toAIA.vgein 129 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 130 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 131 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 132 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 133 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 134 135 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 136 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 137 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 138 csrMod.fromAIA.mtopei.valid := imsic.o.mtopei.valid 139 csrMod.fromAIA.stopei.valid := imsic.o.stopei.valid 140 csrMod.fromAIA.vstopei.valid := imsic.o.vstopei.valid 141 csrMod.fromAIA.mtopei.bits := imsic.o.mtopei.bits 142 csrMod.fromAIA.stopei.bits := imsic.o.stopei.bits 143 csrMod.fromAIA.vstopei.bits := imsic.o.vstopei.bits 144 145 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 146 import ExceptionNO._ 147 exceptionVec(EX_BP ) := isEbreak 148 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 149 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 150 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 151 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 152 exceptionVec(EX_II ) := csrMod.io.out.EX_II 153 //exceptionVec(EX_VI ) := csrMod.io.out.EX_VI // Todo: check other EX_VI 154 155 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 156 157 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 158 val isXRetFlag = RegInit(false.B) 159 isXRetFlag := Mux1H( 160 Seq( 161 DelayN(flush, 5), 162 isXRet, 163 ), 164 Seq( 165 false.B, 166 true.B, 167 ) 168 ) 169 170 flushPipe := csrMod.io.out.flushPipe || isXRet // || frontendTriggerUpdate // Todo: trigger 171 172 // tlb 173 val tlb = Wire(new TlbCsrBundle) 174 tlb.satp.apply(csrMod.io.tlb.satp) 175 // expose several csr bits for tlb 176 tlb.priv.mxr := csrMod.io.tlb.mxr 177 tlb.priv.sum := csrMod.io.tlb.sum 178 tlb.priv.imode := csrMod.io.tlb.imode 179 tlb.priv.dmode := csrMod.io.tlb.dmode 180 181 io.in.ready := true.B // Todo: Async read imsic may block CSR 182 io.out.valid := valid 183 io.out.bits.ctrl.exceptionVec.get := exceptionVec 184 io.out.bits.ctrl.flushPipe.get := flushPipe 185 io.out.bits.res.data := csrMod.io.out.rData 186 connect0LatencyCtrlSingal 187 188 // Todo: summerize all difftest skip condition 189 csrOut.isPerfCnt := csrMod.io.out.isPerfCnt && valid && func =/= CSROpType.jmp 190 csrOut.fpu.frm := csrMod.io.out.fpState.frm 191 csrOut.vpu.vstart := csrMod.io.out.vecState.vstart 192 csrOut.vpu.vxsat := csrMod.io.out.vecState.vxsat 193 csrOut.vpu.vxrm := csrMod.io.out.vecState.vxrm 194 csrOut.vpu.vcsr := csrMod.io.out.vecState.vcsr 195 csrOut.vpu.vl := csrMod.io.out.vecState.vl 196 csrOut.vpu.vtype := csrMod.io.out.vecState.vtype 197 csrOut.vpu.vlenb := csrMod.io.out.vecState.vlenb 198 csrOut.vpu.vill := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VILL.asUInt 199 csrOut.vpu.vma := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VMA.asUInt 200 csrOut.vpu.vta := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VTA.asUInt 201 csrOut.vpu.vsew := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VSEW.asUInt 202 csrOut.vpu.vlmul := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VLMUL.asUInt 203 204 csrOut.isXRet := isXRetFlag 205 206 csrOut.trapTarget := csrMod.io.out.targetPc 207 csrOut.interrupt := csrMod.io.out.interrupt 208 csrOut.wfi_event := csrMod.io.out.wfi_event 209 210 csrOut.tlb := tlb 211 212 csrOut.debugMode := csrMod.io.out.debugMode 213 214 csrOut.disableSfence := csrMod.io.out.disableSfence 215 216 csrOut.customCtrl match { 217 case custom => 218 custom.l1I_pf_enable := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1I_PF_ENABLE.asBool 219 custom.l2_pf_enable := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L2_PF_ENABLE.asBool 220 custom.l1D_pf_enable := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ENABLE.asBool 221 custom.l1D_pf_train_on_hit := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_TRAIN_ON_HIT.asBool 222 custom.l1D_pf_enable_agt := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ENABLE_AGT.asBool 223 custom.l1D_pf_enable_pht := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ENABLE_PHT.asBool 224 custom.l1D_pf_active_threshold := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ACTIVE_THRESHOLD.asUInt 225 custom.l1D_pf_active_stride := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ACTIVE_STRIDE.asUInt 226 custom.l1D_pf_enable_stride := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L1D_PF_ENABLE_STRIDE.asUInt 227 custom.l2_pf_store_only := csrMod.io.customCtrl.spfctl.asTypeOf(new SpfctlBundle).L2_PF_STORE_ONLY.asBool 228 // ICache 229 custom.icache_parity_enable := csrMod.io.customCtrl.sfetchctl 230 // Labeled XiangShan 231 custom.dsid := csrMod.io.customCtrl.sdsid 232 // Load violation predictor 233 custom.lvpred_disable := csrMod.io.customCtrl.slvpredctl.asTypeOf(new SlvpredctlBundle).LVPRED_DISABLE.asBool 234 custom.no_spec_load := csrMod.io.customCtrl.slvpredctl.asTypeOf(new SlvpredctlBundle).NO_SPEC_LOAD.asBool 235 custom.storeset_wait_store := csrMod.io.customCtrl.slvpredctl.asTypeOf(new SlvpredctlBundle).STORESET_WAIT_STORE.asBool 236 custom.storeset_no_fast_wakeup := csrMod.io.customCtrl.slvpredctl.asTypeOf(new SlvpredctlBundle).STORESET_NO_FAST_WAKEUP.asBool 237 custom.lvpred_timeout := csrMod.io.customCtrl.slvpredctl.asTypeOf(new SlvpredctlBundle).LVPRED_TIMEOUT.asUInt 238 // Branch predictor 239 custom.bp_ctrl := csrMod.io.customCtrl.sbpctl.asUInt.asTypeOf(custom.bp_ctrl) 240 // Memory Block 241 custom.sbuffer_threshold := csrMod.io.customCtrl.smblockctl.asTypeOf(new SmblockctlBundle).SBUFFER_THRESHOLD.asUInt 242 custom.ldld_vio_check_enable := csrMod.io.customCtrl.smblockctl.asTypeOf(new SmblockctlBundle).LDLD_VIO_CHECK_ENABLE.asBool 243 custom.soft_prefetch_enable := csrMod.io.customCtrl.smblockctl.asTypeOf(new SmblockctlBundle).SOFT_PREFETCH_ENABLE.asBool 244 custom.cache_error_enable := csrMod.io.customCtrl.smblockctl.asTypeOf(new SmblockctlBundle).CACHE_ERROR_ENABLE.asBool 245 custom.uncache_write_outstanding_enable := csrMod.io.customCtrl.smblockctl.asTypeOf(new SmblockctlBundle).UNCACHE_WRITE_OUTSTANDING_ENABLE.asBool 246 // Rename 247 custom.fusion_enable := csrMod.io.customCtrl.srnctl.asTypeOf(new SrnctlBundle).FUSION_ENABLE.asBool 248 custom.wfi_enable := csrMod.io.customCtrl.srnctl.asTypeOf(new SrnctlBundle).WFI_ENABLE.asBool 249 // Decode 250 custom.svinval_enable := csrMod.io.customCtrl.srnctl.asTypeOf(new SrnctlBundle).SVINVAL_ENABLE.asBool 251 // distribute csr write signal 252 // write to frontend and memory 253 custom.distribute_csr.w.valid := csrWen 254 custom.distribute_csr.w.bits.addr := addr 255 custom.distribute_csr.w.bits.data := wdata 256 // rename single step 257 custom.singlestep := csrMod.io.out.singleStepFlag 258 // trigger 259 custom.frontend_trigger := DontCare 260 custom.mem_trigger := DontCare 261 } 262} 263 264class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 265 val hartId = Input(UInt(8.W)) 266 val setIpNumValidVec2 = Input(UInt(SetIpNumValidSize.W)) 267 val setIpNum = Input(UInt(log2Up(NumIRSrc).W)) 268}